In reply to Avi_311:
SystemVerilog only recognizes the last value of a transition in a cross bin selection.
Normally people do not mix transitions with values in the same bin. The values are redundant in your case. However might be easier to create separate overlapping bins just for making your cross easier to define.
size_cp: coverpoint cov_params.size{
bins s64 = {64};
bins bsize[] = (32=>64,32=>64);
}
channel_cp: coverpoint cov_params.channel{
bins c0 = {0};
bins channel[] = (1=>0,1=>0);
}
channel_size_cross: cross channel_cp, size_cp {
ignore_bins ig = binsof(size_cp.size) || binsof(channel_cp.channel);
}