I am working on a UVM testbench for a top module that includes a register module, an ALU, and a control module. The top module doesn’t have direct outputs but processes instructions internally. I need to verify the internal states of each module to ensure they are functioning correctly based on the instructions sent.
Top Module: Contains register, ALU, and control modules.
Instructions: Sent to the top module for processing.
Objective: Verify the internal states (e.g., register contents, ALU results, control signals) after instruction execution.
but I’m not entirely sure about the best way to access and verify these internal states.