I have a question here. I want to change the parameter value of a module in one test case. This module is instantiated in the test_env. How can I do this?
There are a number of ways to do this depending on how critical overall re-compilation time is for you, and how many different parameter values you need to deal with.
If you want to override the parameter value on the command line and you are using Questa, you can use the -G vsim option. Otherwise you might have to use +define to change the override value from the command line and recompile.
In reply to dave_59:
Dave,
Thanks for your good answer. Now I know I can change the parameter in command line and recompile. But I still have the question. There is only one parameter in a module need to be changed. Because we use a single command stript to run all the testcase, it is preferred that the parameter value can be changed in the source file of the test case. If it is possible?
In reply to sunshine_007:
You will have to elaborate on what you mean by “use a single command script to run all the testcases”. Something on the command line has to be different in order to run a different tests.
And what do you mean by “source file of the testcase”? Is that a module that instantiates the DUT and has an initial block that calls run_test().
In reply to dave_59:
dave,
thanks again.
- “use a single command script to run all the testcases” mean we use a regression script which will run all the test cases under the testcases directory.
- “source file of the testcase” mean the the a systemverilog file. we use the OVM, so the DUT is instantiated in the tb_top. all the testcase is a class which is extend from a base_test. Just like xbus example in the ovm2.0.2. For example
if module xbus_tb_top.sv there is below always to generate clock.
parameter sig_clk_period=5;
//Generate Clock
always
#sig_clk_period xi0.sig_clock = ~xi0.sig_clock;
how to change the parameter sig_clk_period value to 10 in the test case test_read_modify_write which is in the test_lib.sv.