How do I show SV preprocessor output?

OVM
1

I’ve run into some compilation errors in my testbench. OVM uses a lot of preprocessing-macros (`define), so I’m having a hard-time tracking down the offending statements.

Is there a way to tell irun (6.20s004) to dump the SVPP’s output? I tried

irun -log_svpp mylogfile.txt -svpp

, but mylogfile.txt only displays a summary of the files-compiled (not the raw preprocessor output, which is what I need.)

2

Hi,

The svpp output is written to the INCA_libs/irun.lnx86.06.20.nc/svpplib directory - you may have seen error messages related to the files here that svpp generates. These are the “raw” SystemVerilog files that I think you are wanting to see?

Regards,
Dave

3

I checked that inca*/svpplib directory, but the svpp_mod.map is almost empty. It shows the header (“Original File” … “Modified File”), but no actual entries follow.

Sorry, I wasn’t being clear. By “raw” files, I’m referring to the (text ASCII) output of the preprocessor, after all macro-substitutions have been made. I wanted to inspect these files, so I could see the “postprocessed” Systemverilog files, just before the compiler starts crunching them.

Let me see if this example helps:

macro1.sv (original, starting source-file)
`define **SILLY_EXAMPLE( first, second )** first``second
module macro1();

integer x =1;
integer y = 2;
integer xy = 0;

initial begin : main

  **`SILLY_EXAMPLE(x, y)** = x + y;
  $display( "x + y = %d", **`SILLY_EXAMPLE( x, y )** );
  
end : main
endmodule : macro1

After Systemverilog-preprocesser:

module macro1(); // **<-- this is the file I want to see!**

integer x =1;
integer y = 2;
integer xy = 0;

initial begin : main

  ***xy*** = x + y;
  $display( "x + y = %d", ***xy*** );
  
end : main
endmodule : macro1
4

Hi,

The svpp preprocessor is used to translate code that contains parameterized classes to a specialized class for each parameter used. It does not touch macros - these are passed to the compiler (which knows how to process them).

I don’t know if there is a way to get irun to show you the code after macros have been expanded. That is something you will have to ask your Cadence rep.

Regards,
Dave

5

Hi,
The svpp preprocessor is used to translate code that contains parameterized classes to a specialized class for each parameter used. It does not touch macros - these are passed to the compiler (which knows how to process them).

It seems I was looking in the wrong direction, thanks for the clarification!

6

You can use -E outputfile on the vlog command line with Questa.

Dave

7

It seems I was looking in the wrong direction, thanks for the clarification!

To revisit this issue …

Starting in Verdi 2008.01, the source-code browser has the option to do inline-expansion of Verilog/Systemverilog define macros. (Before, you had to move the mouse over the macro, and Verdi would popup the substitution-test.)
This feature is accessed by launching verdi with the command-line variable verdi -macrodebug (and setenv EXPAND_MACRO_DEBUG 1)

Does Simvision have a similar feature? Sometimes I want to see the inline-expansion of `ovm_* macros, because it’s more convenient then keeping multiple editor-windows open.