I have a signal in my design that is tied to ‘1’. Initially, at the start of the simulation, the signal is ‘x’, and later it transitions to ‘1’. I have created separate bins for this signal to capture the values ‘0’ and ‘1’.
I am sampling the signal on a continuous clock, Clock is ‘x’ when signal is in ‘x’ state. I have observed that the bin created for ‘0’ is also being hit, which is unexpected.
If anyone has encountered this issue before, could you please share your insights?