Hitting an unexpected value while sampling a signal tied to a constant in the design

Hi,

I have a signal in my design that is tied to ‘1’. Initially, at the start of the simulation, the signal is ‘x’, and later it transitions to ‘1’. I have created separate bins for this signal to capture the values ‘0’ and ‘1’.

I am sampling the signal on a continuous clock, Clock is ‘x’ when signal is in ‘x’ state. I have observed that the bin created for ‘0’ is also being hit, which is unexpected.

If anyone has encountered this issue before, could you please share your insights?

Thanks & Regards,
Hari

Impossible to help without seeing any code. Is everything declared with 4-state logic?

Hi, Sorry for the late reply, I am talking about the signal ret2n in below code

Please find the below code developed in monitor

  task monitor_low_power_trans();
    memory_trans_item_t lp_trans;
    forever begin
      wait(cfg.enable_trans_mon == 1'b1);
        @(posedge vif.peri_clk);
           collect_lp_cov = 1'b1;
           vif.collect_lp_cov = collect_lp_cov;
        if(collect_lp_cov) begin
         lp_trans = memory_trans_item_t::type_id::create("lp_trans");
         lp_trans.pgen  = vif.pgen;
         lp_trans.ret2n = vif.ret2n;
         lock.get(1);
         mem_trans_ap.write(lp_trans);
         lock.put(1);
        end
    end
  endtask

In Interface it was declared as logic,

  logic                  pgen;
  logic                  ret2n;

In coverage module sampling done as below,

 covergroup mem_pgen_retn_cg;
    option.per_instance = 1;
    option.name = "mem_pgen_retn_cg";

    power_gen : coverpoint mem_trans.pgen;
    retention2 : coverpoint mem_trans.ret2n; 

    pgenXret2n : cross power_gen, retention2; 
  endgroup : mem_pgen_retn_cg

Write function having below logic,

     if (cfg.has_coverage >= 2) begin // {
        mem_trans_addtl_cg.sample();
        mem_pgen_retn_cg.sample();
      end // }

Here, has_coverage is always 2

A wild guess - is your transaction model 2-state? Show us how mem_trans is coded.