Having problem with state transition coverage

*In reply to mmistry@apm.com:*My requirement is , there can be more than 1 (less than 4) transition of (1 => 2) in between 0 and 3.

Consider using an assertion
cover property (a==0 |=> (a==1 ##1 a==2)[*1:4] ##1 a==3);

Ben Ben@systemverilog.us