Getting error in TLM expample

OVM
1

I have one simple example which uses TLM get_port and get_export/get_import and it gives some error while running in Questa 6.6 version.

Please go through the example code and point out the problem.

module tlm_lab;

import ovm_pkg::*;
`include “ovm_macros.svh”

class pkt;
rand bit[31:0] addr;
rand bit[7:0] data;
endclass

class generator extends ovm_component;

pkt p;
ovm_blocking_get_imp #(pkt,generator) gen_tlm;
//ovm_blocking_get_export #(pkt) gen_tlm;

// Constructor - Required syntax
function new(string name, ovm_component parent);
super.new(name, parent);
gen_tlm = new (“gen_tlm”,this);
$write( " generator new called ");
endfunction : new

virtual task get(output pkt pp);
p = new();
assert(p.randomize);
$display(“%p”,pp);
pp = p;
endtask

endclassclass driver extends ovm_component;

pkt dp;
ovm_blocking_get_port #(pkt) drv_tlm ;

// Constructor - Required syntax
function new(string name, ovm_component parent);
super.new(name, parent);
drv_tlm = new (“drv_tlm”,this);
$display( "drive new called ");
endfunction : new

task run();
repeat (10)
begin
dp = new;
drv_tlm.get(dp);
$display(“%p”,dp);
#10;
end
endtask

endclass

class driver extends ovm_component;

pkt dp;
ovm_blocking_get_port #(pkt) drv_tlm ;

// Constructor - Required syntax
function new(string name, ovm_component parent);
super.new(name, parent);
drv_tlm = new (“drv_tlm”,this);
$display( "drive new called ");
endfunction : new

task run();
repeat (10)
begin
dp = new;
drv_tlm.get(dp);
$display(“%p”,dp);
#10;
end
endtask

endclass

generator gen = new("gen",null);
driver drv = new("drv",null);

initial
begin

drv.drv_tlm.connect(gen.gen_tlm);
$display( " CONNECT is called here ");
// connect tlm

drv.run();
 $finish;

end

endmodule

ERROR msg from Questa 6.6

----------------------------------------------------------------

generator new called drive new called

CONNECT is called here

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ns Iteration: 0 Process: /tlm_lab/#INITIAL#64 File: /tools6/Questa6.6/questasim/linux/…/verilog_src/ovm-2.1/src/tlm/ovm_ports.svh

Fatal error in file /tools6/Questa6.6/questasim/linux/…/verilog_src/ovm-2.1/src/ovm_pkg.sv

HDL call sequence:

Stopped at /tools6/Questa6.6/questasim/linux/…/verilog_src/ovm-2.1/src/tlm/ovm_ports.svh 96

called from tlm_lab.sv 52

called from tlm_lab.sv 71

Thanks in Advance.

2 
class env extends ovm_component;

   `ovm_component_utils(env)
   
   generator gen;
   driver    drv;
   
   function new(string name,ovm_component parent=null);
        super.new(name,parent);
   endfunction : new
   
   virtual function void build();
        super.build();
		gen = new("gen",null);
        drv = new("drv",null);
   endfunction : build
   
   virtual function void connect();
        drv.drv_tlm.connect(gen.gen_tlm);
		$display( " CONNECT is called here ");// connect tlm
   endfunction : connect

endclass : env


initial
begin
   env e = new("env");
   run_test();
end
3

@Girisha:

The OVM flow in general has to pass through some phasing while the codes are running, like they have to go through the build phase, connect phase etc…

As those were missing in you code, probably that was the one which was causing you the error…

@Ichip : Smart move dude :-)

Thanks,
Desperado → Its mear fun & Adventure with OVM :p ;) :D

4

Thanks…
This issue is solved by by calling run_test inside initial block.