class ahb_burst; rand int unsigned start_address; rand int unsigned Haddr; rand bit [2:0] Htrans; rand bit [1:0] Hsize; typedef enum{SINGLE=0,UNDEFINED=1,INCR4=2,WRAP4=3,INCR8=4,WRAP8=5,INCR16=6,WRAP16=7} burst_type; rand burst_type type_of_transfer; rand bit [5:0] beats; function…

[image] Regarding function in constraints SystemVerilog In reply to MICRO_91 : User defined functions in constraints do not get in-lined. That is why all those rules about using function in constraints exist. A function body that refers to variables outside the definition…

Execution flow of constraints

SystemVerilog

dave_59 September 6, 2024, 2:23am 2

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