In reply to nitishg:
There is no way from within your testbench environment to disable an entire covergroup except by preventing it from being constructed in the first place. There are tool specific ways of excluding coverage from a covergroup after simulation completes.
From a methodology viewpoint, the best thing would be to embed your covergroups in coverage collecting class, and then from your environment, control whether the class gets constructed and connected to the rest of the your environment. In the OVM/UVM, this would be a component connected to a monitor through an analysis port, or contained in a scoreboard.