BAEILHO
September 27, 2012, 7:34am
1
Hi.
I’m questasim’s user.
I’m verifying my DUT using ovm.
my DUT is memory. and has a inout port.
the problem is below.
module my_tb;
my_IF A_IF;
my_second_IF B_IF;
my_DUT DUT(A_IF);
.
.
always @(A_IF.sys_clk)begin
if(wr_status_st==0) begin
B_IF.data = A_IF.data;
end else begin
A_IF.data = B_IF.data; <<< error
end
end
error message is
“Net is illegal in left-hand side of procedural continuous assignment.”
The following code (modified) compile fine. Didn’t you declare logic/reg for “data” in the interface my_IF?
interface my_IF;
logic data;
logic sys_clk;
endinterface
interface my_second_IF;
logic data;
endinterface
module my_DUT(my_IF A_IF);
endmodule
module my_tb;
logic wr_status_st;
my_IF A_IF();
my_second_IF B_IF();
my_DUT DUT(A_IF);
always @(A_IF.sys_clk)
begin
if(wr_status_st==0)
begin
B_IF.data = A_IF.data;
end
else
begin
A_IF.data = B_IF.data;
end
end
endmodule
dave_59
September 28, 2012, 1:12am
3
In reply to mpattaje :
You cannot make procedural assignments to wires, and inout ports can only be connected to wires. See my DVCon paper: The Missing Link: The Testbench to DUT Connection , especially the section on bidirectional buses.