Defining specific bins

SystemVerilog
2

Thanks for sharing the detailed observation.

I run your code on EDA Playground to verify the behavior, and here’s what I found:

  1. Single Coverpoint with One Dynamic Bin Array
covergroup cov1;
  coverpoint io_size {
    bins p1_five_one_two[] = {[512:262144]} with ( item % 512 == 0 );
  }
endgroup
  • All 512 bins are actually created
  • From p1_five_one_two_00200 [512] to p1_five_one_two_40000 [262144]
  1. Two Dynamic Bin Arrays in One Coverpoint
covergroup cov1;
  coverpoint io_size {
    bins p1_five_one_two[] = {[512:131072]}    with ( item % 512 == 0 );
    bins p2_five_one_two[] = {[131584:262144]} with ( item % 512 == 0 );
  }
endgroup
  • All 512 (p1_five_one_two ->256 and p2_five_one_two ->256)bins are actually created
  • For p1_five_one_two : p1_five_one_two_00200[512] to p1_five_one_two_20000 [131072]
  • And for p2_five_one_two : p1_five_one_two_20200[131584] to p1_five_one_two_40000[262144]
  1. Two Separate Coverpoints
covergroup cov1;
  Lower: coverpoint io_size {
    bins p1_five_one_two[] = {[512:131072]} with ( item % 512 == 0 );
  }
  Upper: coverpoint io_size {
    bins p2_five_one_two[] = {[131584:262144]} with ( item % 512 == 0 );
  }
endgroup
  • Total 512 bins creates (256 for Lower, 256 for Upper)
  • Lower coverpoint : p1_five_one_two_00200[512] to p1_five_one_two_20000[131072]
  • Upper coverpoint : p1_five_one_two_20200[131584] to p1_five_one_two_40000[262144]
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