Adding the ability to create a cross between two separate covergroups is a highly requested enhancement for SystemVerilog. However your particular example demonstrates a major problem with doing so. You are either going to sample cg_for_agent1 OR cg_for_agent2, but not both simultaneously. A cross bin is hit when all the coverpoint bins in is set are hit. So if you are sampling cg_for_agent1, which bins from cg_for_agent2 are part of the cross?