we have bit[999:0] addr variable, when you are randomizing the addr value continuous 7 ones random positions expect remaining bits are zero"0"

Hi @prasanthB1 Please find the link below: [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. FYI, your solution seems to be good too.

Constraint to generate continous 7 ones

SystemVerilog

dave_59 September 30, 2024, 3:05pm 4