Connecting SV assertions to internal signals in VHDL

OVM
1

Hi,
I have a design written in VHDL .I have written system verilog assertions in an external files which uses internal signals of this design.
I have written a testbench in Verilog/SystemVerilog.

When i simulate assertion module is not getting connected to the VHDL module.

I tried bind statement also.

Can any one plz tell me what is the right method to connect SVA to internal signals of VHDL.
thanks

2

VHDL (pre-2008) does not allow you to access internal signals from an external scope.

If you are using QuestaSim, you can try the following:

  1. You can use SignalSpy, which is a Questa-specific capability using C-based functions to gain access to internal signals, similar to Verilog hierarchical pathnames. I think other simulators might have a similar feature.

  2. If your simulator supports VHDL 2008 features, you can now use “external” names in VHDL. Basically, wherever you would use a signal name, you can use external names. The syntax is

<< signal *.path.to.signal* : subtype >>

(the << and >> delimiters are part of the syntax). If you need to use the same external name many times, it pays to use an alias:

alias mysig is << signal .path.to.signal : subtype >>;

QuestaSim version 6.5b supports VHDL 2008 external names. I’m not sure about other simulators.

-Kurt

3

I am using Riviera-Pro from ALDEC.
Is there any simulator independent method.
I read in one of the Ben Cohen’s materials which shows that bind can be used for connecting to internal signals of VHDL design.Is that wrong?
Any ways i dont want to use global package?So plz tell a better way.
thanks

4

Not sure if Riviera-Pro supports SV-bind to VHDL, need to check with their support. But they do have an equiv of SignalSpy called “signal_agent”, see:
http://www.aldec.com/products/Feature.aspx?marketingfeatureid=874be3b3-f281-43e1-be00-73e7a3a69401

We at CVC created a package that wraps these simulator dependent code to a generic one and made it working for NC, MTI & Aldec few years back. I need to dig it around as there have been several disk changes and that tiny code is archived somewhere.

Srini
www.cvcblr.com

5

thanks for the suggestion.
I tried using $signal_agent,but could not compile it.
I used alog -work mylibrary -pli myfile.sv
as recommended in the manual.
Still there is this error which says :
unknowm function $system_signal_agent ,expecting endmodule,end…

What is the problem here.
And srini can you plz send me the code you wrote for aldec thanks.
waris
war_isbest2005@yahoo.com

6

thanks for the suggestion.
I tried using $signal_agent,but could not compile it.
I used alog -work mylibrary -pli myfile.sv
as recommended in the manual.
Still there is this error which says :
unknowm function $system_signal_agent ,expecting endmodule,end…
What is the problem here.
And srini can you plz send me the code you wrote for aldec thanks.
waris
war_isbest2005@yahoo.com

I found it and uploaded to:

http://www.cvcblr.com/downloads/probe_pkg.tgz

But from your description it looks like you need it work on SV-VHDL boundary, we didn’t try that as our Riviera licenses are under renewal stage as of now. What I’ve uploaded at http://www.cvcblr.com/downloads/probe_pkg.tgz is pure VHDL package that will keep your VHDL code SIM independent.

BTW, Kurt’s idea is cool - I can’t wait for more tools to support that VHDL-08 feature!

Srini
www.cvcblr.com