Coding for covergroup with coverpoint and cross

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In reply to davidct:

I’m not sure what do you mean by complicated class or UVM, both are systemverilog coding,

In anyways if your simulator supports 1800-2012 IEEE SV you could create an array with the valid values you want in this case the one hot, something similar to the following


module test();
  
  parameter N = 8;
  bit [N-1:0] values[N]; //this will contain the relevant values you want in your bins
  bit [N-1:0] mode;
  bit enable;
  bit clk;
  
  covergroup cg @(posedge clk);
    
    enable_cp: coverpoint enable;
    
    one_hot_mode_cp: coverpoint mode {
      bins one_hot[N] = values;
    }
    
    cross enable_cp, one_hot_mode_cp;
    
  endgroup
      
  cg m_cg;
  
  initial begin
    forever #10 clk = ~clk;
  end
  
  initial begin
    
    foreach(values[i]) values[i] = 1 << i; //first populate with the one hot values
    m_cg = new; //create the covergroup
    
    repeat (N) begin
      @(posedge clk);
      mode = $urandom_range(2**N-1, 0);
      enable = $urandom_range(1, 0);
      $display("@ %0t mode =  %b enable = %b coverage = %f", $time,  mode, enable, m_cg.get_coverage());
    end
	$finish;
  end
  
endmodule

Keep in mind the order First the values array got populated then the covergroup gets constructed, I guess you could optimise this more.
HTH,
-R