Code for handling asynchronous reset in uvm driver

UVM
2

Try the following ::

task run_phase( uvm_phase phase);

 forever begin

   fork
      detect_rst();
      get_and_drive();  // Has forever loop within the task
   join_any
       // will come here only when reset is asserted
       disable fork;
       wait( reset_n == 1 );  // Wait till reset is de-asserted
  end 
endtask

task detect_rst();
   @(negedge vif.reset_n);
         vif.a <= 0;
         vif.b <= 0;
         vif.in <=0;
endtask

task get_and_drive();
  //forever @(posedge vif.clk) begin  // ORG
  forever begin
      seq_item_port.get_next_item(req);
       @(posedge vif.clk);
      // Drive signals via NBA
        vif.a <= req.a;
        vif.b <= req.b;
        vif.in <=req.in;
      seq_item_port.item_done();
   end
 endtask