In reply to pdonahue_ventana:
It might help if you gave an example of a situation where you have RTL code you want synthesized but never simulated. I can think of plenty of cases for the opposite situation. Code in your testbench that should never get executed should be part of an error or fatal message.
illegal_bins was not meant for find bugs in your DUT. It was more meant for finding problems with you coverage and constraint modules. There is no way to control these kinds of messages or print out diagnosing information like you have with checkers and assertions.