Case () inside gives errors with Cadence ncverilog

Hi,
The following code compiles normally with Questa, but gives an error with ncverilog. Can any one figure out why ?


case (ratio) inside
	     [990 : 1010] :  mon_txn.bit_rate_captured  = 3'b000;
	     [390 :410]   :  mon_txn.bit_rate_captured  = 3'b001;
	     [190 :210]   :  mon_txn.bit_rate_captured  = 3'b010;
	     [90 : 110]   :  mon_txn.bit_rate_captured  = 3'b011;
	     [35 : 45]    :  mon_txn.bit_rate_captured  = 3'b100;
	     [16 : 24]    :  mon_txn.bit_rate_captured  = 3'b101;
	     [8 : 12]     :  mon_txn.bit_rate_captured  = 3'b110;	     
endcase

(1)case (ratio) inside
ncvlog: *E,ILLPRI: illegal expression primary [4.2(IEEE)]
(2) [990 : 1010] : mon_txn.bit_rate_captured = 3’b000;
|
ncvlog: *E,NOTSTT : expecting a statement [9(IEEE)]
(3) [390 :410] : mon_txn.bit_rate_captured = 3’b001;
|
ncvlog: *E,ILLPRI : illegal expression primary [4.2(IEEE)].
(4) [390 :410] : mon_txn.bit_rate_captured = 3’b001;
|
ncvlog: *E,NOTSTT : expecting a statement [9(IEEE)].
and so on

In reply to Mustafa:

What version of Incisive are you using? I know case-inside was not supported for some 12.x versions, but it seems to be supported for 13.x. Contact Cadence.