Cannot compile an interface definition inside a module

OVM
1

Hello,

I am trying to follow the OVM/UVM cookbook article Bus Functional Models
The idea of defining an interface inside a module seemed OK, until I tried to compile it with VCS (Synopsys) or NCVerilog (Cadence) - it doesn’t work for me - they both complain that interface definition inside a module is not supported. To summarize, I entered the following code:

module my_module;
  reg my_reg;
  interface my_if;
    logic my_sig;
  endinterface
endmodule

This compiles successfully only on Model/QuestaSim but not on the other two major compilers/simulators. Is there an alternative to that BFM integration approach?

Thanks,
Stefan Yankov

2

The wishbone_bus_bfm_if in the example does not have to be declared inside the wb_bus_wrapper. Verilog hierarchical search rules for task and function calls will resolve the wrapper calls.

3

In reply to dave_59:

Hi Dave,

Can you please give example code?
I tried adding a hierarchical path in the interface definition to the BFM but I get warnings from VCS and NCVerilog about the hierarchical references made.
I was looking for a way to clean these warnings up and I tried the Cookbook code (interface nested in module) but it doesn’t work for me.
I would like to see a working example.

Thanks,
Stefan