In reply to aksistla:
You can accomplish what you want in SystemVerilog, however there are several thing to note about your pseudo code.
Arguments that will change value during the life of the covergroup and those changes need to seen inside the covergroup need to be passed by reference (the same is true with a task call).
covergroup CG(ref bit condition, bit [2:0] cp1) @(posedge clk iff condition);
Both condition and cp1 will now be passed by reference.
The iff construct in a covergroup, coverpoint, or bins construct does not control the existence of an instance of a covergroup, coverpoint, it only gates the sampling of the bins.
Finally, try to use arrays instead of naming individual instances inst_0, inst_1.