Cadence IUS SV randomization

OVM
1

Hello All,

I face one interesting thing while simulating my testbench.

[A] code:

module TB;
config_item c1=new();
intiial begin
c1.randomize();
end
endmodule

**code:

module TB;
[B]byte a; // new**
config_item c1=new();
intiial begin
c1.randomize();
end
endmodule

In [A] and [B] , only difference is “byte a”.

When I am simulating [A] code with seed=1 , I get some random values in config item.
While I am simulating [B] code with seed=1, I get different random values in config item.

Though there is only one change of “byte a”, why I am getting different random values??.

Thanks in advance,

Best Regards,
Ankit Sheth

2

Tool’s random number generator is function of ( code , seed value ).

so we can also say that
random value = f( code , seed value )

if the code changes random value generated will also changes.

Please correct me. if i am wrong.

3

Hi Ankit Sheth,

The First thing,

As I can get from your codes, Code [A] and Code [B] are same except one change that is inclusion of byte b in Code [B].

And I am able to understand that the config_item is same in both the codes as per your words.

I think there shouldn’t be any change in the random values bcoz:

  1. To generate random values the variables should be declared as “rand” or “randc”, here in your code the inclusion of byte b in Code [B] is not going to make any big difference since, both the config_item in both codes are same.

  2. Generation of random values are tool dependent, each tool will give different values bcoz it depends on there architecture design of the “pseudo random number generator”. And when you force the pseudo random generator to generate with a specific value, the tool will give the same random values when you run the codes again. By default the tool is given with a seed value of “0”.

  3. From your code as there is no change in the config_item, and since your are forcing the seed value to be same for both the codes, the values shoudnt be different.

It would be fine if you check your config_item of both the codes bcoz if there is a change in them then values might differ.

Wish you got the point…

Thanks,
Desperado ;)

4

saravanansha, you are not correct. SystemVerilog is designed to provide some level of random stability to prevent code changes from disturbing random number generation.

One thing to consider in ankit’s example is that c1is a static variable with an initialization. Like most programming languages, the order of static variable initialization is undefined and not recommended unless there are no other dependencies involved.

Dave

5

Hi Dave,

In SystemVerilog seeding will be done hierachily. Every module instance, interface instance, program instance and package has initialization RNG. Every thread and object has independent RNG .

byte a;

a is object of type byte.

do “a”'s RNG has any influence ?

Thanks and Regards
Saravanan

6

Hello All,

After doing various exercises I came to conclusion that randomization is changed if we add any new variable in testbench with initialization , is this correct?

Example 1:

module top();

bit success;

class config_item;

rand bit [10:0] a;
rand int b;
rand longint c;

function post_randomize();
$display(“The value of a=%d \n b=%d \n c=%d \n”,a,b,c);
endfunction

endclass

config_item c1=new();
initial
begin
success=c1.randomize();
end

initial
begin
#500;
$finish();
end
endmodule

When I ran the above example with irun -sv -svseed 1 top.sv . I got following randomization .

SVSEED set from command line: 1
The value of a= 576
b= -288430883
c= -7018109888101937654

Now I just initilize the success variable and randomization is changed.
Example 2:

module top();

bit success=0;

class config_item;

rand bit [10:0] a;
rand int b;
rand longint c;

function post_randomize();
$display(“The value of a=%d \n b=%d \n c=%d \n”,a,b,c);
endfunction

endclass

config_item c1=new();
initial
begin
success=c1.randomize();
end

initial
begin
#500;
$finish();
end
endmodule

When I ran the above example with irun -sv -svseed 1 top.sv . I got following randomization .

SVSEED set from command line: 1
The value of a=1465
b= 530015039
c= -7851834468401277769

Please clarify my doubt.

Best Regars,
Ankit Sheth

7

Responding to Saravanan,

Sometimes, the code you think is the problem has nothing to do with it. This is a static initialization order problem. For example

module top;
  config_obj c1 = new();
   **byte b;**
  config_obj c2 = new();
  initial begin
      assert (c1.randomize());
      assert (c2.randomize());
end
endmodule

Simulators (whether it be IUS or Questa) do not guarantee any particular ordering or stability of static initialization. So when you add the declaration of b, there could be a change in the random stability of c1 and c2.

If you change the code to

module top;
  config_obj c1;
   **byte b;**
  config_obj c2;
  initial begin
      c1 = new();
      c2 = new()
      assert (c1.randomize());
      assert (c2.randomize());
end
endmodule

This will be stable on any simulator.

Dave

8

Hi Dave,

As you mentioned I tried with the following example,

module top();

class config_item;
rand bit [10:0] a;
randc bit [15:0] b;
rand longint c;

function post_randomize();
$display(“The value of a=%d \n b=%d \n c=%d \n”,a,b,c);
endfunction
endclass

config_item c1
bit success;
config_item c2;
initial
begin
c1 = new();
c2 = new();
success=c1.randomize();
success=c2.randomize();
end

initial
begin
#500;
$finish();
end
endmodule

This is the Output what I got.

SVSEED set from command line: 1
The value of a=1512
b= 4272
c= -7018109888101937654

The value of a=1965
b=37346
c= 2846876738273993664

Here both c1 and c2 randomization is different. I ran this on IUS tool.
Best Regards,
Pinal Patel