AXI Read Strobes!


In AXI3 protocol, there are no Strobe bits for AXI Reads unlike AXI Writes.
Hence, If any processor just does a 32-bit Read from memory, who has the control logic to fetch appropriate 32-bit data from the 128-bit wide memory data bus??

Points to note -

  1. The processor does a 32-bit Read from memory.
  2. Memory data bus width is 128-bits.
  3. Read address is aligned to 32-bits (4 bytes), but is not aligned to 128-bits (16 bytes).
  4. Since the Read address is not aligned to 128-bits (16 bytes), the Memory data bus contains 128-bits data corresponding to the Read address aligned to 128-bits (16 bytes).

For example (to explain 4.), If processor does a 32-bit read from memory address 0x6000_0008 (32-bit or 4-bytes aligned Read address), the memory Read data bus fetches 128-bit Read data starting from address 0x6000_0000 (128-bits or 16 byte aligned Read address). Now how does the Processor know which 32-bits is the valid data for the Read address 0x6000_0008?

In reply to Vignesh Raghavan:

The processor is sending the address 0x6000_0008…so it knows from which data to read…because the ARADDR AND ARLEN is send by the processor itself…so it knows which data to be read and from which address…no need for read strobe…because master knows from where to read and it considers that as a valid byte only!!

In reply to

Thanks Sagar…