Automate testbench-DUT connection code

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Overview:
This package automatically generates the code required to connect UVM testbench classes to DUT signals.

Features:

  1. Allow signals to be defined as “normal” class members (i.e. not as part of an interface)
  2. Hide away the actual connection code and HDL details such as Verilog/VHDL, reg/wire etc. All the user has to do is configure the ports to connect to the right language and right net type.
  3. Allow users to use strings/string manipulation to specify signal names
  4. Allow users to work with relative signal names
  5. Allow generated code to either use virtual interfaces or “two kingdoms” (configurable)

How does it work?

  1. Define signals in classes such as monitors/drivers (or anywhere else)
  2. Configure the HDL path to point to the right signal name
  3. Run 0 to generate the connection code
  4. Compile the connection code
  5. Run again with the connection code loaded as another top

For actual commands just look in sim/Makefile

To run:
cd sim
make all

File Download:

automatic_tb_dut.tar.gz