Assertion using Generate Block

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In reply to dave_59:

Hi Dave,

    Thanks for the suggestion. I have tried with small example, however i did mistake in my example.

the OP has mentioned that assignments are not happening in generate block.But the fact is that variable assignment has to happen in procedural blocks so problem is not with the generate block.

Here is my example , i should have realized what was the actual problem in OP code.




module test;
bit [63:0]TX_DATA[3];
genvar    i;
  
generate
for ( i = 0; i < 3; i++)
  begin
     initial
	begin
	   TX_DATA[i] = 64'b1 << i;
	   $display("the value=%0b",TX_DATA[i]);
	end
  end
   
endgenerate
   
endmodule // test