Applying Reset during Simulation

OVM
1

I am verifying a DUT with OVM methodology… I want to check the DUT functionality when Reset is applied… But if I give reset my environment also has to come to its initial state… (i mean if I am in the middle of any sub sub sub sub… sequence, i want to come out immediately by collapsing all processes)…

Is there any seperate Reset handling in OVM :rolleyes:. Please Help me…

Thanks in advance,
Leela Krishna.

2

Are you using e or systemverilog?

If you’re using e there are predefined macros and methodologies to handle the reset phase. See section 6 of the OVM user guide “Testflow phases”

If you are using SystemVerilog the methodology is much less evolved,
but you can try to emulate techniques from e.

Typically with a reset you may want to check

  1. DUT output signals are reset : this can be done using assertions, or on reset_start {check that}
  2. Check registers are reset. So a reset_end event you can reset your testbench register model and start a register read sequence.
  3. Check internal FSMs FIFOs have been cleared. After register read sequence send more data in/out of DUT to check it was reset properly.

Hope that helps.

3

Hi…
Typically reset is applied in the initial state but my requirement is to apply reset to DUT and simultaneously to the verification environment in the middle of simulation. Applying reset to DUT is straight forward but my environment contains a chain of ovm_sequences running and there i am finding problem.
I think U got my prob…!!:confused: