Hello,
Is it possible to have a coverpoint or a cover property that covers the transition of one signal to another signal, respecting UVM rules? (I use a uvm_subscriber to extend a new class for my coverage)
For example, I have three bit signals “A”, “B” and “C”. I want to cover that afer the assertion and deassertion of signal “A” I will eventually have the assertion of “B” and not the assertion of “C”. And similarly, after the assertion of “B” I will eventually have the assertion of “C” and not of “A”.
I though about something like:
covergroup mySignals;
//cover set and reset
coverpoint A {
bins set_A = {1};
bins reset_A = {0};
}
coverpoint B {
bins set_B = {1};
bins reset_B = {0};
}
coverpoint C {
bins set_C = {1};
bins reset_C = {0};
}
//cover transition, option1:
coverpoint ({A,B}) {
bins trans_A2B = (2'b10 => 2'b01):
ignore_bins trans_B2A = (2'b01 => 2'b10); // that helps to now if there is any count, but it does not check that this transition must not occur
}
endgroup
But the problem that I see with this option is that it will only counts when the transition is in the next clock cycle, not in the future. Another option that I have seen is:
//option2:
cover property (a&&!b |=> ##[1:5] b);
But this option cannot go inside of the class.
Can you help me?
Please if you did not understand my problem ask what you need!
Thanks!!