Turn off constraint block across all extended classes of a common parent class

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1 

class base_const;
  rand int x;

  constraint c1 {
    x == 10;
  }
endclass
 
class child1_const extends base_const;
  rand int x;

  constraint c1 {
    x == 20;
  }
endclass

class child2_const extends base_const;
  rand int x;

  constraint c1 {
    x == 30;
  }
endclass

module top_const;
 base_const base;
 child_const child1;
 child1_const child2;

  initial begin
    base = new();
    child1 = new();
    child2 = new();
    
    base.c1.constraint_mode(0);
    child1.c1.constraint_mode(0);
    child2.c1.constraint_mode(0);

    base.randomize();
    child1.randomize();
    child2.randomize();
  end
endmodule

Instead of calling 'constraint_mode(0) for each of the extended classes, I want to turn of constraint mode for all ‘n’ extended classes in a single line of code. Is it possible?

2

In reply to vinodrm:

There is nothing built into SystemVerilog to do this for you.

What you can do is define a non-rand mode bit in your base class, and write all your extended constraints as an implication of that mode.