Not able to cover all bins

Coverage
1

Hi,

I am running below code but my coverage is not 100% eventhoush i am driving all possible opcodes.
//////////////////////////////////////////////////////////////////////////

program main;
    bit clk=0;
  class Transaction;
    typedef enum {ADD,SUB,MULT,DIV} opcode_e;
    rand opcode_e opcode;
    rand bit [7:0] op1;
    rand bit [7:0] op2;
    
    constraint my_c{
      op1>op2;
    } 
    covergroup covcode@(posedge clk);
     cp:coverpoint opcode;
    endgroup:covcode
    function new();
     covcode=new(); 
    endfunction:new
    task mytask;
      @(posedge clk)
      $display("Present simulation time is %t",$time);
    endtask:mytask
    function mylogic();
      if(opcode==0)
        return(op1+op2);
      else if(opcode==1)
        return(op1-op2);
      else if(opcode==2)
        return(op1*op2);
      else 
        return(op1/op2);
    endfunction:mylogic
  endclass
  initial begin
    Transaction tr;
    repeat(5) begin 
      tr=new();
      tr.randomize(); 
      tr.mylogic; 
      $display("My transaction is %p",tr);
    end
    tr.mytask;
  end
  initial begin 
    forever 
      #2 clk=~clk;
  end
  initial 
   #1000 $finish; 
endprogram:main

//////////////////////////////////////////////////////////////////////////
output is:

My transaction is '{opcode:ADD, op1:251, op2:248, covcode:{ref to covergroup #covcode#}}

My transaction is '{opcode:MULT, op1:56, op2:46, covcode:{ref to covergroup #covcode#}}

My transaction is '{opcode:ADD, op1:61, op2:51, covcode:{ref to covergroup #covcode#}}

My transaction is '{opcode:DIV, op1:232, op2:167, covcode:{ref to covergroup #covcode#}}

My transaction is '{opcode:MULT, op1:227, op2:40, covcode:{ref to covergroup #covcode#}}

But my coverage is 50% only,Not able to understand the reason of it.

Thanks

2

In reply to TransVerif:

Assuming this is experimental code only, so no comments on style/use model. Your problem is around:

repeat(5) begin
  tr=new();
  tr.randomize();
  tr.mylogic;
  $display("My transaction is %p",tr);
end

Your sampling is @(posedge clk) - your generation (above) is 0-time. Insert a clock delay there as well and see.

HTH
Srini
www.go2uvm.org

3

In reply to Srini @ CVCblr.com:

Hi Srini,

I am able to cover all bins by adding delay in initial block.

Can you suggest related to use model/Style what you mentioned.

Regards
Bharath