How to increase code coverage

hello all,
iam verifying the SRAM code with verilog testbench and iam compiling the code with “vcs -cm line+tgl+cond+fsm filenames.v”.
but iam getting coverage report only 60%(codecoverage).
it was not hitting at the “write and read logic”.
can i know how to increase the codecoverage…?

thanks in advance…

In reply to RC:

The short answer is “Write more tests”

The complete answer would fill volumes. You can start here: Coverage/Code Coverage Metrics | Verification Academy

In reply to dave_59:

Thanks dave…