Hi,
How can we write functional coverage for verilog testbench.i can write cover-groups inside a module and trigger cover groups,apart from this is there any standard apporach?
Thanks in Advance,
Nawaz
The standard approach for writing testbenches with functional coverage is to use a monitor that sends transactions to a coverage collector with the UVM. Just because your testbench is Verilog (which is just SystemVerilog without classes) does not prevent you from adding a class based monitor.