Error

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1

When I try to simulate the verification code I got an error like this … Any body help me?

Fatal: (vsim-3695) C:/questasim_6.5a/examples/counter_verification.sv(0): The interface port ‘intf’ must be passed an actual interface.

2

You are running a very old version of Questa and I could not find this example in the release directory.

You cannot leave an interface port unconnected, or you made the wrong connection to an interface port.

3

Hi Dave,

You cannot leave an interface port unconnected

I got a similar error when I just compile it, but not instantiate it. Why is that?

4

You need to show some code and the exact error message.

5

The error meesage is as below.

Fatal: (vsim-3695) The interface port ‘mif’ must be passed an actual interface.

And I have the below module compiled, without instantiating it.

module mbus_ctrl (
mbus_if mif
);

// content

endmodule

6

This might be a tool specific compilation command-line issue. Sometimes modules you compile but don’t instantiate become automatically instantiated as top-level module instances.

This Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. You should read your tool’s. User Manual or contact your tool vendor directly for support.

7

Thanks for the explanation. But I was using questasim2022.1_1.