Eliminating transition bins by using with condition?

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1

Hi All,

can transition bins can be eliminated by using ‘with’ condition. I have tried but i am getting an error.

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In reply to saikishore_154567:

No. The “with” condition only specifies values. You can only ignore transition bins that match another transition. SystemVerilog’s transition coverage is very basic. You might try other methods of capturing this kind of coverage using an assertion.

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In reply to dave_59:

Thanks Dave!