Q there is a base packet named TS through which two packets are extended namely TS1 & TS2 (child classes). In ts1 and ts2 some variables are defined which is not in ts(parent class). I want to write covergroup of ts in which i will write bins of ts1 and ts2. Basically i want to access variables of ts1 and ts2 (means parent class wants to access variables of child class). So what should i do, i mean casting or any kind of class assignment?
In reply to tech_savvy:
You can use the concept of Forward Referencing.
For Example :
If there are two classes c1 and c2 and c1 is declared before c2, to access the handle of c2, you can use the above concept.
typedef class c2;
class c1;
c2 c; //using class c2 handle before declaring it.
endclass
class c2;
c1 c;
endclass
More information can be found at the below link:
https://verificationacademy.com/forums/systemverilog/forward-refrencing
In reply to tech_savvy:
You need to be careful when using the terms ‘parent’ and ‘child’. In UVM, a ‘parent’ will instantiate a ‘child’, which is normally a completely different type. In this regard, what Nitish recommended is correct.
In your case, you are dealing with base classes and extended classes. In this case, there is no way to access any additional variables in an extended class when using a base class handle.
You can $cast the variable to a handle for the extended class, but I would recommend creating a new covergroup for the variables in the extended class.