hi
i have question about assertion
when valid signal is high after 5 cycle ready signal is high how to write in assertion code in particular condition
In reply to Vaishali Dangashiya:
Taking your description literally it would be written as
assert property ( @ (posedge clk) valid |-> ##5 ready;)
The reads “Whenever valid is high, ready must also be high 5 clock cycles later”
But what is missing is it OK for ready to be high less than 5clock cycles later? And is it just the first occurence of valid being high that matters?