Are you a Design or Verification Engineer or Manager interested in Low Power Verification?
Low Power Verification Forum
This seminar will explore the new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.
Date, Time & Location:
- Thursday, September 12th
- 11:30 AM - 4:00 PM US/Pacific
- El Segundo, CA
- Low Power Considerations for Verification
- Measuring and Driving Lowest Power from C to RTL to Gate
- Enabling Early Low Power Design Verification and Analysis Using Emulation
- Productive Low Power Debug Across All Engines and Flows
Learn more and register.