UVM Common Phases

The common phases are the set of function and task phases that all uvm_components execute together.  All uvm_components are always synchronized with respect to the common phases.

The common phases are executed in the sequence they are specified below.

Contents
UVM Common PhasesThe common phases are the set of function and task phases that all uvm_components execute together.
uvm_build_phaseCreate and configure of testbench structure
uvm_connect_phaseEstablish cross-component connections.
uvm_end_of_elaboration_phaseFine-tune the testbench.
uvm_start_of_simulation_phaseGet ready for DUT to be simulated.
uvm_run_phaseStimulate the DUT.
uvm_extract_phaseExtract data from different points of the verficiation environment.
uvm_check_phaseCheck for any unexpected conditions in the verification environment.
uvm_report_phaseReport results of the test.
uvm_final_phaseTie up loose ends.

uvm_build_phase

Create and configure of testbench structure

uvm_topdown_phase that calls the uvm_component::build_phase method.

Upon entry

  • The top-level components have been instantiated under uvm_root.
  • Current simulation time is still equal to 0 but some “delta cycles” may have occurred

Typical Uses

  • Instantiate sub-components.
  • Instantiate register model.
  • Get configuration values for the component being built.
  • Set configuration values for sub-components.

Exit Criteria

Summary
uvm_build_phase
Create and configure of testbench structure
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_topdown_phase
uvm_build_phase
Class Declaration
class uvm_build_phase extends uvm_topdown_phase

uvm_connect_phase

Establish cross-component connections.

uvm_bottomup_phase that calls the uvm_component::connect_phase method.

Upon Entry

  • All components have been instantiated.
  • Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

  • Connect TLM ports and exports.
  • Connect TLM initiator sockets and target sockets.
  • Connect register model to adapter components.
  • Setup explicit phase domains.

Exit Criteria

  • All cross-component connections have been established.
  • All independent phase domains are set.
Summary
uvm_connect_phase
Establish cross-component connections.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_bottomup_phase
uvm_connect_phase
Class Declaration
class uvm_connect_phase extends uvm_bottomup_phase

uvm_end_of_elaboration_phase

Fine-tune the testbench.

uvm_bottomup_phase that calls the uvm_component::end_of_elaboration_phase method.

Upon Entry

  • The verification environment has been completely assembled.
  • Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

  • Display environment topology.
  • Open files.
  • Define additional configuration settings for components.

Exit Criteria

  • None.
Summary
uvm_end_of_elaboration_phase
Fine-tune the testbench.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_bottomup_phase
uvm_end_of_elaboration_phase
Class Declaration
class uvm_end_of_elaboration_phase extends uvm_bottomup_phase

uvm_start_of_simulation_phase

Get ready for DUT to be simulated.

uvm_bottomup_phase that calls the uvm_component::start_of_simulation_phase method.

Upon Entry

  • Other simulation engines, debuggers, hardware assisted platforms and all other run-time tools have been started and synchronized.
  • The verification environment has been completely configured and is ready to start.
  • Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

  • Display environment topology
  • Set debugger breakpoint
  • Set initial run-time configuration values.

Exit Criteria

  • None.
Summary
uvm_start_of_simulation_phase
Get ready for DUT to be simulated.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_bottomup_phase
uvm_start_of_simulation_phase
Class Declaration
class uvm_start_of_simulation_phase extends uvm_bottomup_phase

uvm_run_phase

Stimulate the DUT.

This uvm_task_phase calls the uvm_component::run_phase virtual method.  This phase runs in parallel to the runtime phases, uvm_pre_reset_phase through uvm_post_shutdown_phase.  All components in the testbench are synchronized with respect to the run phase regardles of the phase domain they belong to.

Upon Entry

  • Indicates that power has been applied.
  • There should not have been any active clock edges before entry into this phase (e.g. x->1 transitions via initial blocks).
  • Current simulation time is still equal to 0 but some “delta cycles” may have occurred.

Typical Uses

  • Components implement behavior that is exhibited for the entire run-time, across the various run-time phases.
  • Backward compatibility with OVM.

Exit Criteria

  • The DUT no longer needs to be simulated, and
  • The <uvm_post_shutdown_ph> is ready to end

The run phase terminates in one of two ways.

1.  All run_phase objections are dropped

When all objections on the run_phase objection have been dropped, the phase ends and all of its threads are killed.  If no component raises a run_phase objection immediately upon entering the phase, the phase ends immediately.

2.  Timeout

The phase ends if the timeout expires before all objections are dropped.  By default, the timeout is set to 9200 seconds.  You may override this via uvm_root::set_timeout.

If a timeout occurs in your simulation, or if simulation never ends despite completion of your test stimulus, then it usually indicates that a component continues to object to the end of a phase.

Summary
uvm_run_phase
Stimulate the DUT.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_task_phase
uvm_run_phase
Class Declaration
class uvm_run_phase extends uvm_task_phase

uvm_extract_phase

Extract data from different points of the verficiation environment.

uvm_bottomup_phase that calls the uvm_component::extract_phase method.

Upon Entry

  • The DUT no longer needs to be simulated.
  • Simulation time will no longer advance.

Typical Uses

  • Extract any remaining data and final state information from scoreboard and testbench components
  • Probe the DUT (via zero-time hierarchical references and/or backdoor accesses) for final state information.
  • Compute statistics and summaries.
  • Display final state information
  • Close files.

Exit Criteria

  • All data has been collected and summarized.
Summary
uvm_extract_phase
Extract data from different points of the verficiation environment.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_bottomup_phase
uvm_extract_phase
Class Declaration
class uvm_extract_phase extends uvm_bottomup_phase

uvm_check_phase

Check for any unexpected conditions in the verification environment.

uvm_bottomup_phase that calls the uvm_component::check_phase method.

Upon Entry

  • All data has been collected.

Typical Uses

  • Check that no unaccounted-for data remain.

Exit Criteria

  • Test is known to have passed or failed.
Summary
uvm_check_phase
Check for any unexpected conditions in the verification environment.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_bottomup_phase
uvm_check_phase
Class Declaration
class uvm_check_phase extends uvm_bottomup_phase

uvm_report_phase

Report results of the test.

uvm_bottomup_phase that calls the uvm_component::report_phase method.

Upon Entry

  • Test is known to have passed or failed.

Typical Uses

  • Report test results.
  • Write results to file.

Exit Criteria

  • End of test.
Summary
uvm_report_phase
Report results of the test.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_bottomup_phase
uvm_report_phase
Class Declaration
class uvm_report_phase extends uvm_bottomup_phase

uvm_final_phase

Tie up loose ends.

uvm_topdown_phase that calls the uvm_component::final_phase method.

Upon Entry

  • All test-related activity has completed.

Typical Uses

  • Close files.
  • Terminate co-simulation engines.

Exit Criteria

  • Ready to exit simulator.
Summary
uvm_final_phase
Tie up loose ends.
Class Hierarchy
uvm_void
uvm_object
uvm_phase
uvm_topdown_phase
uvm_final_phase
Class Declaration
class uvm_final_phase extends uvm_topdown_phase
virtual class uvm_component extends uvm_report_object
The uvm_component class is the root base class for UVM components.
class uvm_build_phase extends uvm_topdown_phase
Create and configure of testbench structure
class uvm_connect_phase extends uvm_bottomup_phase
Establish cross-component connections.
class uvm_end_of_elaboration_phase extends uvm_bottomup_phase
Fine-tune the testbench.
class uvm_start_of_simulation_phase extends uvm_bottomup_phase
Get ready for DUT to be simulated.
class uvm_run_phase extends uvm_task_phase
Stimulate the DUT.
class uvm_extract_phase extends uvm_bottomup_phase
Extract data from different points of the verficiation environment.
class uvm_check_phase extends uvm_bottomup_phase
Check for any unexpected conditions in the verification environment.
class uvm_report_phase extends uvm_bottomup_phase
Report results of the test.
class uvm_final_phase extends uvm_topdown_phase
Tie up loose ends.
The uvm_void class is the base class for all UVM classes.
virtual class uvm_object extends uvm_void
The uvm_object class is the base class for all UVM data and hierarchical classes.
class uvm_phase extends uvm_object
This base class defines everything about a phase: behavior, state, and context.
virtual class uvm_topdown_phase extends uvm_phase
Virtual base class for function phases that operate top-down.
virtual function void build_phase( uvm_phase  phase )
The uvm_build_phase phase implementation method.
The uvm_root class serves as the implicit top-level and phase controller for all UVM components.
virtual class uvm_bottomup_phase extends uvm_phase
Virtual base class for function phases that operate bottom-up.
virtual function void connect_phase( uvm_phase  phase )
The uvm_connect_phase phase implementation method.
virtual function void end_of_elaboration_phase( uvm_phase  phase )
The uvm_end_of_elaboration_phase phase implementation method.
virtual function void start_of_simulation_phase( uvm_phase  phase )
The uvm_start_of_simulation_phase phase implementation method.
virtual class uvm_task_phase extends uvm_phase
Base class for all task phases.
virtual task run_phase( uvm_phase  phase )
The uvm_run_phase phase implementation method.
class uvm_pre_reset_phase extends uvm_task_phase
Before reset is asserted.
class uvm_post_shutdown_phase extends uvm_task_phase
After things have settled down.
function void set_timeout( time  timeout,   
bit  overridable  =  1 )
Specifies the timeout for the simulation.
virtual function void extract_phase( uvm_phase  phase )
The uvm_extract_phase phase implementation method.
virtual function void check_phase( uvm_phase  phase )
The uvm_check_phase phase implementation method.
virtual function void report_phase( uvm_phase  phase )
The uvm_report_phase phase implementation method.
virtual function void final_phase( uvm_phase  phase )
The uvm_final_phase phase implementation method.