uvm_reg_hw_reset_seq

Test the hard reset values of registers

The test sequence performs the following steps

1. resets the DUT and the block abstraction class associated with this sequence.

2. reads all of the registers in the block, via all of the available address maps, comparing the value read with the expected reset value.

If bit-type resource named “NO_REG_TESTS” or “NO_REG_HW_RESET_TEST” in the “REG::” namespace matches the full name of the block or register, the block or register is not tested.

uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
                           "NO_REG_TESTS", 1, this);

This is usually the first test executed on any DUT.

Summary
uvm_reg_hw_reset_seq
Test the hard reset values of registers
Class Hierarchy
uvm_reg_sequence#(uvm_sequence#(uvm_reg_item))
uvm_reg_hw_reset_seq
Class Declaration
class uvm_reg_hw_reset_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Variables
modelThe block to be tested.
bodyExecutes the Hardware Reset sequence.
Methods
reset_blkReset the DUT that corresponds to the specified block abstraction class.

Variables

model

The block to be tested.  Declared in the base class.

uvm_reg_block model;

body

virtual task body()

Executes the Hardware Reset sequence.  Do not call directly.  Use seq.start() instead.

Methods

reset_blk

virtual task reset_blk( uvm_reg_block  blk )

Reset the DUT that corresponds to the specified block abstraction class.

Currently empty.  Will rollback the environment’s phase to the reset phase once the new phasing is available.

In the meantime, the DUT should be reset before executing this test sequence or this method should be implemented in an extension to reset the DUT.

class uvm_reg_hw_reset_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Test the hard reset values of registers
virtual task body()
Executes the Hardware Reset sequence.
virtual task reset_blk( uvm_reg_block  blk )
Reset the DUT that corresponds to the specified block abstraction class.