“We are now uniquely positioned as Siemens EDA to provide more value beyond our traditional EDA competitors and help our customers verify their systems and chips well into the future.”
Welcome to this very special edition of Verification Horizons! As many of you are aware, Mentor Graphics was acquired by Siemens a few years ago, and things were finally completed earlier this year. That means that we are now Siemens EDA, and I am excited to share with you – for the first time in Verification Horizons – some of what you can expect to see as a result of this process. I recently spoke with Ravi Subramanian, our Senior VP of IC Verification Solutions, to get his take on all the great things we’ve been able to accomplish since officially becoming Siemens EDA. He told me that the Siemens acquisition a few years ago gave us a unique opportunity to invest in our traditional product portfolio and to build solutions combining the best of our Mentor heritage with the breadth of Product Lifecycle and other key technologies from Siemens. Combined with the resources to acquire complementary tools, technologies, and solutions, we are now uniquely positioned as Siemens EDA to provide more value beyond our traditional EDA competitors and help our customers verify their systems and chips well into the future.
Perhaps the highest profile move we made was our acquisition of OneSpin Solutions. To help answer some of the questions I’m sure many of you have about this merger, I interviewed my old friend, Harry Foster, our Chief Scientist for Verification and my new friend, Dominik Strasser, co-founder of OneSpin, to get their thoughts on the many ways we can now work together to provide solutions for our customers in a variety of industries. I’d like to take this opportunity to welcome Dominik and the whole OneSpin team to the Siemens EDA family.
One of the really exciting aspects for me of being part of Siemens is our strong commitment to the idea of a “digital twin” where the goal is to simulate not just a chip, but also the whole system in which the chip will operate. In a way, this is kind of like what I’ve been doing in coming up with new ways to model the environment in which a chip will operate (which we have traditionally viewed as a testbench), but taken to a much higher level. Think about simulating a chip as part of an assembly that controls a critical piece of a fighter jet that’s engaged in a dogfight, and making sure that the whole aircraft performs as required, or simulating the chip as part of a self-driving car that has to communicate with all the other cars and the traffic lights, as well as recognize road signs and pedestrians. Well, Siemens has thought about that, and in “Digital Thread, Digital Twin, and IC Development,” my friend Ray Salemi and Lisa Murphy explain how all of that will actually work.
The digital twin is explored in a little more detail in “Addressing the Trends and Challenges of Automotive IC Development,” by my colleague Ann Keffer. This article highlights how the digital twin, through the integration of our Functional Safety solutions with the Siemens Xcelerator portfolio of software and services, lets you verify and validate a vehicle and its subsystems in a variety of scenarios.
Our next article, by several of my Siemens colleagues and our friend Tammy Reeve of Patmos Engineering, one of the recognized experts in the DO-254 standard for verification of airborne electronics, looks at “Deploying HLS in a DO-254/ED-80 Workflow”. HLS helps “shift left” much of the verification, and this article helps show how to take advantage of that fact in a way compatible with DO-254.
Next, we have a trio of articles highlighting our Hardware-Assisted Verification (HAV) solutions. We begin with Jean-Marie Brunet, Senior Director in our Scalable Verification Solutions Division, and Lauro Rizatti, a well-respected HAV expert, taking us on a tour of “HW Assisted Verification Through the Years.” This retrospective highlights the strengths and weaknesses of emulation versus FPGA prototying, and how the two have evolved to become highly complementary in recent years. Then in “Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive,” Jean-Marie shows us how our Veloce Strato emulators and Veloce Primo FPGA prototyping system give you an integrated solution that lets you trade off speed for design visibility in a unified flow. We end this section with “Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs” by my friend Steve Bailey and Antonio Costa, where they take us on a journey of how to meet requirements and accelerate time-to-market on a High-Performance Computing Artificial Intelligence SoC design. Steve and Antonio build on Jean-Marie’s article and go into more depth specifically on the FPGA prototyping side of the equation.
Our next two articles highlight some great new capabilities in our Visualizer Debug Environment, starting with “Hug the Debug – Before It’s Too Late” by my colleague Sumit Vishwakarma. This first article shows how we’ve integrated analog, real-number modeling and mixed-signal debug in Visualizer along with all of the powerful digital and testbench debug features that many of you have come to know and love. Then, in “Questa Visualizer Adds Coverage Analysis to the Platform,” my colleague Yara Esam walks us through a new coverage-centric approach to debug. By elevating coverage to a “first-class” view in Visualizer, you can now use the debugger to focus your efforts proactively on closing coverage holes, including starting with a coverage view of your design and clicking through to see where in the design the problem lies and why it’s a problem to begin with.
In “Verifying a DDR5 Memory Subsystem,” my colleagues Raman Jain and Kamlesh Mulchandani introduce some of the issues that arise in trying to verify the new high-speed DDR5 memory protocol using our latest Questa Verification IP (QVIP) solution. Raman and Kamlesh walk us through actually using the DDR5 QVIP to make sure that your system can handle the increased complexity.
We round out the tool-centric set of articles with “Expediting Simulation Turnaround Time with Incremental Build Flows” by my friend Neil Johnson, where he looks at how best to organize your files and use the unique compilation abilities in Questa to let you get back into simulation as quickly as possible if you need to make a design change. And last, but not least, my long-time friend and colleague (even before our Mentor/Siemens days) Dave Rich, reminds us that, even as we’ve become Siemens EDA, we continue our commitment to standards development. As always, we support standards because we remain confident that we can provide superior tools and solutions for our users compared with our competitors. Now that we are Siemens EDA, that commitment and confidence will only grow stronger.
On a closing note, you’ll notice that this issue of Verification Horizons is the first we’ve ever done that is completely on-line. We hope you like this new format and look forward to hearing any feedback you may have. Since DAC has been postponed to December, where we plan to have our next issue available, I’ll just take this opportunity to wish you all a great summer. Thanks for checking out Verification Horizons again, and I hope we’ll be able to be together in person soon.
Editor, Verification Horizons
Back to Top