Verification Horizons Complete Issue:
Verification Horizons Articles:
by Tom Fitzpatrick, Editor and Verification Technologist, Mentor Graphics Corporation
As I write this, my daughter is preparing for the opening night performance of Disney's "Peter Pan" with her youth theater group. Megan is featured as a mermaid and a Native American in the show, and in order to get pictures and video of her performance, I attended the dress rehearsal last night. This is our third season with the group, and I once again helped with set construction. I bring this up for two reasons. The first is to once again indulge your patience in my displaying a little fatherly pride in my daughter's theatrical accomplishments, and the second is to talk about reuse.
Yes, that's right: reuse.
by Prashant Dixit, Questa VIP Product Team, Mentor Graphics
Functional verification is critical in the development of today's complex digital designs. Increasing hardware complexity generally tracks Moore's Law; however, verification complexity grows at an even faster rate. Verification cycle is widely acknowledged as the major bottleneck in design methodology. Up to 70 percent of design time and resources are spent on functional verification. And yet, functional bugs are the number one cause of silicon re-spins.
Another aspect of verification comes into play during integration and system-level verification by the customer once the IP is integrated into a System on Chip (SoC). One of the most time consuming aspects of SoC verification is creating a testbench that models the SoC's interfaces, which can include DDR, Ethernet, USB, PCI Express, and many others.
A better option is to use a commercial verification IP solution that models all interfaces as components that can be plugged into an SoC testbench and simulated along with the chip. This in turn reduces risk and improves time-tomarket for both IP vendors and customers. Verification Intellectual Properties (VIPs) accelerate the chip design and verification cycle with higher reliability, and lower risk and cost.
by David Aerne and Ankur Jain, Verification Technologists, Mentor Graphics
The challenges inherent in verifying today's complex designs are widely known. Verification IP (VIP) helps address these challenges assuming it meets a wide range of requirements. For example, it needs to be proven, provide checks to ensure protocol compliance, provide a comprehensive compliance test suite, and include the ability to collect and analyze coverage. It should also be straightforward to instantiate, configure and exercise, thus minimizing the time to productive verification. Questa Verification IP, part of the Mentor Enterprise Verification Platform, meets these requirements by providing a collection of features referred to as EZ-VIP.
EZ-VIP features easy-to-use connectivity modules, onestop configuration, quick-starter kits and portable utility sequences. This article demonstrates these features while referencing the PCIe and AXI4 Questa VIP components.
by Amit Kumar Jain, Questa VIP Product Team, Mentor Graphics
In a multi-processor system, a cache coherence protocol is vital to maintaining data consistency between local caches and the main memory. With the local processor cache, the bus stimulus must be compliant with the cacheline state in the local cache, and must follow predefined ordering rules between the read/write and cache snoop stimulus. These constraints can make it confusing to generate stimulus on a cache coherent interface. This article addresses such stimulus generation issues by providing easy to use generic APIs along with a cache controller.
by Josh Rensch, Application Engineer, Mentor Graphics
How design engineers can get verification engineers to stop complaining, and other advice.
Hey you, verification engineer. Yeah, you. Are you tired of how long it takes you to figure out what the design is supposed to do? How much time it takes to jury-rig up all the pieces of the verification environment only to be told that isn't what is supposed to be tested in the first place? Well, this article is for you.
by Raghu Ardeishar and Rich Edelman, Verification Technologists, Mentor Graphics
UVM was designed as a means of simplifying and standardizing verification which had been fragmented as a result of many methodologies in use like eRM, VMM, OVM. It started off quite simple. Later on, as a result of feature creep, many of the issues with the older methodologies found its way into UVM. This article looks at some of those issues and suggests ways of simplifying the verification environment.
by Sundar Raman Arunachalam, Senior Software Engineer, VeriKwest Systems
The stimulus control thread also needs to be handled properly so as to determine what needs to happen after a reset is encountered (typically the entire traffic needs to be re-generated). Here traffic includes the sequences required to initialize the DUT before the actual test activity is carried on. In UVM, the concept of phase jumps can provide a solution to this problem. However phase jump is undergoing changes in the UVM technical committee. While several solutions have been proposed for handling reset problems in the past, an AXI-like environment can be tricky and often require additional insights. This article describes techniques for modeling UVM testbench components in an AXI-based environment. It also covers handling the stimulus generation unit (uvm_test) required to re-generate the DUT traffic without using phase jumps. Note that this technique can be applicable to other UVM-based testbench environments.
by Dr. Mike Bartley, CEO, Suresh Babu, Solutions Architect, and Shyam Ramaswamy, Sales and Business Development Manager, TVS
Debug is one of the major bottlenecks that verification teams face today. Traditionally, to make the debug task easier, significant effort is invested upfront by following standard coding guidelines and writing code that is debug friendly. The near-universal adoption of UVM has, while making the verification process a lot more streamlined, however, increased the debug challenge. While most verification engineers understand how to use the UVM library, in a verification environment, the know-how about the implementation of classes and utilities comprising the UVM library like Factory, Sequencer, Random Sequence Library, etc. is limited. Even though some verification teams make use of utility functions built into UVM for accelerating debug, it still represents a significant challenge and consumes a major portion of the verification effort.
To tackle this problem, Questa has incorporated a UVM debug feature which provides a bunch of utilities to easily identify UVM testbench holes. One of the main capabilities that this feature provides is the ability to bring out UVM testbench/VIP variables to the waveform window. Users can also view all the UVM messages required for debug in a single window that provides active links to the source code and waveforms. Questa provides a completely unified system that has everything needed to understand and fix SystemVerilog and UVM testbench/VIP problems.