“We...are now Siemens EDA. This is a huge milestone for us as a company and we hope it will prove to be even more significant for our industry as a whole.”
Welcome to our DVCon U.S. 2021 edition of Verification Horizons! You’ll notice that a few things look different about this issue, and that’s because we are no longer Mentor Graphics, but are now Siemens EDA. This is a huge milestone for us as a company and we hope it will prove to be even more significant for our industry as a whole, giving us the opportunity to share so much more with you.
I’m writing this note to you on Groundhog Day. For those of you not familiar with the particular American phenomenon, on Groundhog Day, February 2nd, the groundhog comes out of his hole and looks around. If he sees his shadow, he goes back in his hole and we get six more weeks of winter. If he doesn’t see his shadow, he stays out and we get an early spring. Of course, Groundhog Day is also the backdrop for the movie of the same name, considered by many to be a masterpiece of both comedy and philosophy, in which Bill Murray plays Phil Connors, a cynical weatherman who gets stuck living the same day over and over again until he eventually learns what it means to live well.
I don’t want to spoil the movie if you haven’t yet seen it (and if you haven’t, you should rent/buy/stream it as soon as possible!), but the central message is that, even when faced with the same situation over and over again, it is always our choice how to react in that situation, and we can always choose to do things better. As verification engineers, we have a similar choice. It’s only when we take full advantage of our resources, stretch beyond our comfort zone, and focus on the right goals that we achieve success.
It also happens to be the ten-year anniversary of the Universal Verification Methodology (UVM) this month (last month by the time you read this). This is a significant milestone for our industry, and a sobering reminder for me personally of the passage of time. In “Celebrating 10 Years of the UVM,” my Siemens colleague Mark Peryer, who has been an integral member of the UVM Working Group for many years, takes a stroll down memory lane to share his reflections on where UVM came from and where it’s going.
Next up, my colleagues from our Questa Verification IP team share their thoughts on “Purging CXL Cache Coherency Dilemmas”. This article introduces us to the Compute Express Link (CXL), which is a new high-speed interconnect that multiplexes between different protocols to support heterogeneous processing and memory systems for high-performance computing environments. This article gives a great overview of CXL and the challenges of cache coherency verification. Check it out to see how our CXL QVIP can help you meet these challenges.
We start our Partners’ Corner section with “What is “Verification” in the Context of DO-254 (Avionics) Programs?” from our friends at Patmos Engineering Services. If you thought you knew what “verification” means, and are looking at verifying any kind of airborne electronics – where a malfunction could lead to death – you’ll want to check out this article to see the additional steps that DO-254 requires to show that something has been verified.
Next, we have a few articles on Formal Verification, starting with “Formal Etiquette for Code Coverage Closure” from our friends at VerifWorks. Like everything else, Coverage Closure is subject to the “80/20 rule” where it’s those last few coverage holes that take up most of the time. This article gives a great overview of Questa CoverCheck, which brings Formal Verification under the hood to help identify which of your remaining coverage holes are real, and which are actually unreachable and so can be automatically excluded.
The rule of thumb for Formal Verification is generally that it’s good for control logic but not for arithmetic or datapath logic, usually due to state-space explosion and complexity. In “A Formal Verification Technique for Complex Arithmetic Hardware,” our friends at Imagination Technologies share with us their technique of abstracting away the details that usually cause formal tools to fail. By cleverly proving consistency over time and showing that a piece of logic is always deterministic, they can formally prove the correctness of large arithmetic systems.
We follow that up with “Predictable and Scalable End-to-End Formal Verification” from our friends at Axiomise. Here you’ll learn how to build on the idea of abstraction for both data and time, which can be applied to reduce the proof complexity and let your Formal tool handle deep sequential blocks, including complex bus protocols, cache-coherent systems, and RISC-V processor designs. Using a straightforward FIFO design, you’ll learn the valuable techniques that you can apply on your own designs.
Next, our friends at Logic Fruit give us “Enabling RISC-V Based System Development,” in which they show us how to assemble a simulation-based verification environment for an open-source customizable RISC-V core-based design. The article walks you through an actual design that you can run on your own to see how a real verification environment would work.
Last, but not least, our friends at Imperas Software build on the idea of RISC-V verification with “The Six Steps of RISC-V Processor Verification Including Vector Extensions.” Since RISC-V is open-source, you can easily add to the instruction set, but those extensions also have to be verified. This article walks you step-by-step through the process of setting up everything you’ll need to assemble an architectural validation test suite for the new standard vector extension set by applying a “step and compare” approach using a golden reference model of the processor.
In these difficult times, I hope that you’ll find this issue of Verification Horizons to be entertaining and informative. I realize that many of you are not able to get out as we once did, and I for one will miss the opportunity to attend DVCon in person this year.
If you need a laugh, I recommend watching the movie “Groundhog Day.” And until we’re able to be together again, remember the words of Phil Connors, “Don’t drive angry!”
Editor, Verification Horizons
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