by Tom Fitzpatrick, Editor and Verification Technologist
"That's what we do as verification engineers, isn't it? We identify problems with a system, trace them back to root causes, fix the root causes and then make sure that everything still works."
As I write this, we're experiencing yet another winter storm here in New England. It started this morning, and the timing was fortuitous since my wife had scheduled a maintenance visit by the oil company to fix a minor problem with the pipes before it really started snowing heavily. While the kids were sleeping in due to school being cancelled, the plumber worked in our basement to make sure everything was working well. It turned out that he had to replace the water feeder valve on the boiler, which was preventing enough water from circulating in the heating pipes. Aside from being inefficient, this also caused the pipes to make a gurgling sound, which was the key symptom that led to the service call in the first place. As I see the snow piling up outside my window (6-8 inches and counting), it's easy to picture the disaster that this could have become had we not identified the problem early and gotten it fixed.
That's what we do as verification engineers, isn't it? We identify problems with a system, trace them back to root causes, fix the root causes and then make sure that everything still works. I'm reminded of my early logic classes when the teacher demonstrated and and or gates with pipes and valves. And being up against a tapeout deadline isn't all that different from fixing a heating system before a winter storm hits. Although the stakes are different in these two scenarios, it's ultimately productivity that matters.
Since I'm the editor, and I can do these kind of things, I've decided to start this issue off with our "Partners' Corner" section. We'll start off with "Don't Forget the Little Things That Can Make Verification Easier" by our friend Stu Sutherland, of Sutherland HDL, and one of the best Verilog and SystemVerilog trainers around. In this article, Stu reminds us that SystemVerilog is more than a verification language – it includes many synthesizable design constructs that clearly specify the designer's intent. These constructs can be employed to avoid common errors and make verification more productive by keeping your focus on verifying the functionality of your design without having to track down what are typically thought of as "low-level bugs."
Our next partner article, by our friends at SmartPlay Technologies, presents a case study showing the advantages of using the Unified Power Format (UPF) standard with Questa Ultra. After a quick overview of the importance of power gating in low-power designs, you'll see how Questa was able to model the behaviors from their UPF specification, and how they were able to debug the power control logic that resulted.
Our friends at Intellitech are next up with "Using Mentor Questa for pre-silicon validation of IEEE 1149.1-2013 based Silicon Instruments" in which they introduce cool new flow for verifying FPGAs, SoCs and other silicon devices. The IEEE 1149-2013 standard is sort of like "JTAG on steroids" and lets you verify the functionality of the actual chip through what Intellitech calls "silicon instruments." The article shows how their NEBULA tool lets you drive your simulation in Questa to use these instruments to drive your simulation, so you can be confident that your post-silicon verification efforts will be as productive as possible.
Our last partner article comes from our friends at eInfochips. In "Dealing With UVM and OVM Sequences" you'll learn how to write reusable sequences in UVM (and OVM) to increase your productivity by making it easy to add new sequences to your testbench. Here you'll learn some practical steps to take to avoid "painting yourself into a corner" as you design your sequences.
We're also happy to have a couple articles from my Mentor Graphics colleagues in this issue. In "Stories of an AMS Verification Dude: Putting Stuff Together," Martin Vlach, our Analog/Mixed-Signal Chief Technologist, gives a rather unconventional view of AMS verification which we hope will give you an understanding of the different levels of abstraction used in digital and analog simulation, and how to connect digital and analog subsystems together.
And last but not least, we have "Portable VHDL Testbench Automation with Intelligent Testbench Automation" by my colleague Matthew Ballance, in which we see how Questa inFact can be used make VHDL testbench environments more productive through the inclusion of intelligent automation. Without having to add anything to the VHDL language, inFact can be used to specify a wide variety of scenarios that can easily be run from a VHDL testbench, but the underlying automation in inFact provides randomization and coverage capabilities that are not possible in VHDL. By raising the level of test specification using inFact, the test specification becomes reusable and portable to other verification environments, like SystemVerilog and UVM.
If you're reading this edition of Verification Horizons at DVCon, I really hope it's not snowing. Please come by the Mentor Graphics booth to say "hi" or look for me in the tutorials and paper sessions. I always enjoy hearing feedback from our readers on how we can keep improving this newsletter. And if you're not at DVCon, I hope that winter is dying down for you and that everyone was able to stay safe and warm. And if you're in the southern hemisphere, I'll wish you a warm safe winter in our DAC issue. I promise.
Editor, Verification Horizons
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