“Think of this edition of Verification Horizons
as a home-delivery service for verification
—Tom Fitzpatrick, on the impact of COVID-19
As I write this, we are well into our third month of lockdown, which I’m sure has altered the way most of you work. I say “you” because I have been blessed to work from home for the majority of my career, so other than not traveling as much as I used to, I haven’t really experienced a huge disruption in my professional life.
On the personal side, I’ve gone through the same as most of you, including having my college-age children finishing up their semester online (although it was nice having them home more than normal). Before the kids came home, my wife and I started using one of those home meal delivery services, where you order online and they send you all the ingredients to prepare the dinner yourself. Since my wife is usually the chef in our family, this has given me a great opportunity to expand my culinary skills and give her a well-deserved break. Once the kids came home, we suspended the service but by that time I’d built up a sizable repertoire of meals I am able to prepare (beyond pasta, French toast, tacos and the occasional stir-fry). All I have to do now is choose the meal and then buy the right items at the grocery store (and pay considerably more to feed my 22-year-old son!) and we’re good to go.
Think of this edition of Verification Horizons as a home-delivery service for verification technology. There may be some things you haven’t tried before, and you might think they’ll taste a little weird, but trust me that you’ll find them deliciously filling. Of course, for some of you, a few of the articles may feel a little like “comfort food,” but even then I’m sure that you’ll taste something new that will make you appreciate it all over again.
We begin with “Formal Is The ‘New Normal’ – Deploy These FV Apps In Your Next Project” from our friends at VerifWorks and CVC. If you’ve never used a formal tool before, this will give you a good overview of several Questa® Formal Apps and how best to apply them in your verification flow. I particularly like the differentiation the authors make between Specification-Driven and Implementation-Driven formal verification applications.
We continue our exploration of formal verification with “Understanding the SVA Engine Using the Fork-Join Model” by our long-term contributor Ben Cohen, a noted formal verification expert. In a follow-up to his article from our March, 2018 issue, Ben takes us through a detailed analysis of how multi-threaded assertions actually work by modeling them as forkjoined
SystemVerilog tasks. This obviously isn’t how the tools actually evaluate the assertions, but by using a mechanism we’re all familiar with, Ben clearly explains what’s going on under the hood of such tools.
In “Bridging the Portability gap for UVM SPI VIP Core reuse from IP to Sub System and SoC using Portable Stimulus,” our friends at Silicon Interfaces show how the new Portable Stimulus Standard can be used to create UVM sequences for a VIP Core that can be reused in multiple contexts. In this article, you’ll see how to model basic block-level operations in PSS for an SPI VIP, and understand how these can be leveraged at the subsystem and SoC levels.
We approach verification IP from a slightly different angle in “PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Application” from our friends at PLDA. If you’ve ever wanted to know more about PCIe, this article gives a great overview of the protocol and the operational modes of Mentor’s Questa® VIP PCIe component. With that understanding, the article provides a nice case study of PLDA’s experience in using the QVIP component to verify their own scalable PCIe controller soft IP component.
We shift gears a bit to take a look at “Extending SoC Design Verification Methods for RISC-V Processor DV” from our friends at Imperas Software. With RISC-V cores now available from multiple vendors as well as in-house designs, including the ability to customize the instruction set, the ability to ensure that your core – the heart of your entire system – functions correctly becomes paramount. The article lays out a few verification flows that can be used to do just that. The key to it all is having a reliable and flexible reference model to serve as the golden model for the processor core, which is what Imperas does.
Another gear shift brings us to “Addressing VHDL Verification Challenges with OSVVM” from wellknown VHDL advocate Jim Lewis of SynthWorks Design. The Open-Source VHDL Verification Methodology is Jim’s vehicle for bringing some of the capabilities available in SystemVerilog, like constrained-random stimulus and functional coverage, to the VHDL community. Whether you’re a VHDL fan or not, you’ll find some really interesting ideas in OSVVM for how to organize tests and testbenches and begin introducing these important capabilities to that community.
We close this issue with “Effective Verification Method of Safety Mechanism Compliant with ISO 26262” from our friends at Verification Technology. As you know, safety-critical designs have the important requirement that if something goes wrong, nobody dies. Given that, the ability to build safety mechanisms into the design to avoid that outcome is critical, as is verifying that the safety mechanisms actually function correctly to ensure that the design can recover gracefully from single-point or latent hardware failures. This article lays out in great detail how to set up your verification environment to make sure that your design will be able to handle such faults.
Normally, I would end my Editor’s Note for our DAC edition with an invitation to stop by our booth at DAC to say hi, but I can’t do that this year since the conference will be online. Instead, I’ll just invite you to check out verificationacademy.com to see all the great content we have there, including past issues of Verification Horizons. There are also many great videos including online training classes, webinars and partner presentations from last year’s DAC. I’m sure the online DAC program will be as informative as always, and this year you can check it all out while you’re cooking something new for dinner. Bon appétit!
Editor, Verification Horizons
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