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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
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    • Methodologies

      • UVM - Universal Verification Methodology
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      • Planning, Measurement, and Analysis
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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      • Coverage Forum

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured Webinars

      • Exhaustive Scoreboarding - 9/28/21
      • CDC Philosophy - 10/12/21
      • Improving Initial RTL Quality
      • Hardware Emulation Productivity
      • Early Identification of Security Vulnerabilities
      • Productive USB4 Verification

    • On-Demand Library

      • Equivalence Checking for FPGA
      • Verification of PCIe IP
      • Advancements in UPF 3.1
      • Three CDC Glitches
      • Optimizing Constraints
      • Fault Campaign for Mixed-Signal
      • All On-Demand Webinars

    • Recording Archive

      • Preparing for PCIe 6.0: Parts I & II
      • Verification Forum 2021: Automotive Functional Safety
      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Visualizer Debug Environment
      • All Recordings

    • Conferences & WRG

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      • DVCon 2020
      • DAC 2019
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    • Siemens EDA Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
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    • Verification Horizons Publication

      • Verification Horizons - September 2021
      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
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    • Training

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  • Home
  • Verification Horizons
  • July 2020
  • What do Grubhub®, Doordash®, and Verification Technology Have in Common?

What do Grubhub®, Doordash®, and Verification Technology Have in Common?

Verification Horizons - Tom Fitzpatrick, Editor

| Verification Horizons - July 2020 by Tom Fitzpatrick, Editor and Verification Technologist

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“Think of this edition of Verification Horizons as a home-delivery service for verification technology.”—Tom Fitzpatrick, on the impact of COVID-19

As I write this, we are well into our third month of lockdown, which I’m sure has altered the way most of you work. I say “you” because I have been blessed to work from home for the majority of my career, so other than not traveling as much as I used to, I haven’t really experienced a huge disruption in my professional life.

On the personal side, I’ve gone through the same as most of you, including having my college-age children finishing up their semester online (although it was nice having them home more than normal). Before the kids came home, my wife and I started using one of those home

...

Table of Contents

Verification Horizons Articles:

  • What do Grubhub®, Doordash®, and Verification Technology Have in Common?

  • Formal Is The “New Normal” - Deploy These FV Apps In Your Next Project

  • Understanding the SVA Engine Using the Fork-Join Model

  • Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC Using Portable Stimulus

  • PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Application

  • Extending SoC Design Verification Methods for RISC-V Processor DV

  • Addressing VHDL Verification Challenges with OSVVM

  • Effective Validation Method of Safety Mechanism Compliant with ISO 26262

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