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  • Verification Horizons
  • February 2012 | Volume 8, Issue 1

February 2012 | Volume 8, Issue 1

Verification Horizons - Tom Fitzpatrick, Editor

Verification Horizons Complete Issue:

  • Download  Verification Horizons - February 2012 | Volume 8, Issue 1 - Hi-Resolution Download - 32.8 MB

Verification Horizons Articles:

Planning, Contingencies, and Constrained-Random Stimulus...in the Kitchen

by Tom Fitzpatrick, Editor and Verification Technologist, Mentor Graphics Corporation

Our featured articles in this issue introduce two new UVM initiatives that we think you'll find useful. Both are intended to extend UVM accessibility to new groups of users. The first article, "Introducing UVM Connect," by my friend and colleague Adam Erickson, gives an introductory look at our open-source UVM Connect library, which provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components, as well as a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). The library makes it possible to use UVM in a mixed-language environment in which the strengths of each language can be applied to the problem as needed. Planning, Contingencies, and Constrained-Random Stimulus...in the Kitchen.

Introducing UVM Connect

by Adam Erickson, Verification Technologist, Mentor Graphics Corporation

So what does this new capability allow you to do? UVM Connect enables the following use models, all designed to maximize IP reuse: Abstraction Refinement— Reuse your SystemC architectural models as reference models in UVM verification. Reuse your stimulus generation agents in SystemVerilog to verify models in SystemC. Expansion of VIP Inventory—More off-the-shelf VIP is available when you are no longer confined to VIP written in one language. Increase IP reuse! To properly verify large SoC systems, verification environments are becoming more of an integration problem than a design problem. Leveraging language strengths—Each language has its strengths. You can leverage SV's powerful constraint solvers and UVM's sequences to provide random stimulus to your SC architectural models. You can leverage SC's speed and capacity for verification of untimed or loosely timed system-level environments. Access to SV UVM from SC—The UVM Command API provides a bridge between SC and UVM simulation in SV. With this API you can wait for and control UVM phase transitions, set and get configuration, issue UVM-style reports, set factory type and instance overrides, and more. Introducing UVM Connect

Automation Management: Are You Living a Scripted Life?

by Darron May, Manager of Verification Analysis Solutions, Mentor Graphics Corporation

Increasing demand for high quality IP and SoC designs and ever shortening design cycles puts pressure on IP and SoC houses to leverage automation as much as possible throughout the entire electronic design and verification processes. This is indeed widely seen in the verification space, where verification engineers have to contend with tasks such as coverage closure, bug hunting, smoke and soak testing, all of which are done through running lots of regressions. How automation is applied to a verification process can have a massive impact (positive and negative) on overall productivity of that process.  Are You Living a Scripted Life?

Efficient Project Management and Verification Sign-off Using Questa Verification Management

by Suresh Babu P., Chakravarthi M.G., Test and Verification Solutions India Pvt. Ltd.

Test and Verification Solutions (TVS) uses Questa Verification Management (Questa VM) for both project management and verification sign off for its asureVIP development program. Questa VM can manage verification data, process and tools with features such as testplan tracking, trend analysis, results analysis and run management. TVS has benefitted specifically from Questa VRM (Verification Run Manager), which automates regression runs and monitors coverage status. These features are useful in helping us identify a bug during a regression run, immediately starting the debug process and subsequently easily monitoring project status. Efficient Project Management and Verification Sign-off Using Questa Verification Management

Using Formal Technology To Improve Coverage Results

by Roger Sabbagh, Product Marketing Manager Design Verification & Harry Foster, Chief Verification Scientist, Mentor Graphics

Debugging continues to be one of the biggest bottlenecks in today's design flow. Yet, when discussing the topic of debugging among project teams, the first thought that comes to mind for most engineers is related to the process of finding bugs in architectural and RTL models, as well as verification code and test. However, debugging touches all processes within a design flow—including the painful task of coverage closure. In fact, one of the most frustrating aspects of debugging is tracking down a particular coverage item that has not been hit only to learn that the coverage item is unreachable. In this article we explore the debugging aspect of coverage closure; with a focus on the unique ability of formal technology to automatically generate simulation exclusion files to improve coverage results while reducing the amount of time wasted trying to hit unreachable states. Using Formal Technology To Improve Coverage Results

Hiding the Guts

by Ray Salemi, Senior Verification Consultant, Mentor Graphics

We verification test bench designers are happy sausage makers, merrily turning out complex and powerful verification environments. To us, object-oriented programming environments not only greatly enhance our productivity, but they make us feel smarter. Who doesn't like to throw around words such as extend, factory, and, of course, polymorphism. It's good for the ego and the soul.

However, our test writing coworkers, the ones who will use our environment to drive stimulus into the DUT, look upon object oriented programming as a horrible goo, that some people need to touch to make the sausages, but that they would rather ignore. When you tell these folks, "Just extend the basic test class, and override the environment in the factory", they look at you as if you had asked them to plunge their hands into a bowl of freshly ground pork. Hiding the Guts

A Methodology for Advanced Block Level Verification

by Ashish Aggarwal, Verification Technologist and Ravindra K. Aneja, Verification Technology Manager, Mentor Graphics

This paper outlines the process for advanced verification methods at the block level. Design and verification issues can be divided into four major categories, each of which we briefly address in this paper: RTL development, verification of standard protocol interfaces, end-to-end verification using a simulation-based environment, and effective management of coverage closure. A Methodology for Advanced Block Level Verification

← Back to Verification Horizons

Planning, Contingencies, and Constrained-Random Stimulus...in the Kitchen

Planning, Contingencies, and Constrained-<br />
Random Stimulus...in the Kitchen by Tom Fitzpatrick, Editor and Verification Technologist

Tom Fitzpatrick
"Our kitchen renovation is nearly complete... Just as with verification, the key is to have a plan,... take as many contingencies into account as you can,...and... be able to handle constrainedrandom stimulus."

—Tom Fitzpatrick

Welcome to the 2012 DVCon issue of Verification Horizons. If you're receiving this issue at DVCon, I hope you enjoy the conference. For the rest of you, you're missing a great week, so please try and attend next year.

Our kitchen renovation is nearly complete. It took us a while to choose the right color for the hardwood floors, but the floor was installed last week. I'm writing this note from a nearby hotel room where my family is camped out for four days while the floor is stained and finished, which is a rather pungent process. Although my children are excited by the hotel's amenities (there is a heated indoor pool, a boon in the middle of a New England winter), it's actually turned out to be quite an exercise in logistics and planning. It's not really a vacation, because I'm still working and the kids are still going to school, gymnastics (Megan) and karate (David). That means that we all had to plan to bring everything we'll need for a typical week, especially since we can't get back in the house until the floors are done. It turns out that, since we decided to extend the hardwood down the hall from the kitchen to the front door, there's no path from outside to anywhere useful in the house. So, if we forgot something (so far, so good!), we're out of luck. Fortunately, I am blessed to be married to one of the foremost planners/project managers you're ever likely to meet.

Just as with verification, the key is to have a plan (my wife is an inveterate list-maker), take as many contingencies into account as you can (we've even got my daughter's pet fish with us!) and, given that David and Megan were responsible for their own things, be able to handle constrained-random stimulus. It's still the first day, but things are looking good so far. If you're at DVCon, I'll be happy to tell you how the week ends.

Our featured articles in this issue introduce two new UVM initiatives that we think you'll find useful. Both are intended to extend UVM accessibility to new groups of users. The first article, "Introducing UVM Connect," by my friend and colleague Adam Erickson, gives an introductory look at our open-source UVM Connect library, which provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components, as well as a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). The library makes it possible to use UVM in a mixed-language environment in which the strengths of each language can be applied to the problem as needed.

The second featured article is extracted from the "UVM/OVM Online Methodology Cookbook" on VerificationAcademy.com and introduces UVM Express, a step-by-step approach that design engineers can use to adopt UVM incrementally. You'll find more details in the Cookbook, but the extracted article discusses how UVM Express helps you move to a transaction-based abstraction level for your tests, and to add functional coverage and constrained-random stimulus in a low-impact, VIP-based manner. By leveraging pre-existing VIP, the designer can enhance his methodology without having to know a lot about UVM or OOP, and will then be well-positioned to move to full UVM if needed.

In our next article, Darron May concludes his three-part series on Verification Management in "Automation Management: Are You Living a Scripted Life?" In this installment, Darron shows how the Questa Verification Run Manager (VRM) reduces the maintenance burden of CAD teams while maximizing throughput and efficiency of large regression suites. Tied to the Unified Coverage Database (UCDB), VRM can automatically rerun tests with the same tool settings, as well as automate the distribution of large jobs across your server farm. When coupled with the other Verification Management capabilities explained previously, this comprehensive solution can provide a 20x improvement in verification productivity.

Our Partners' Corner article this time comes from our friends at Test and Verification Solutions who describe how to achieve "Efficient project management and verification sign-off using Questa Verification Management." They'll show you how they used VRM and the testplan tracker to manage their regression system, specifically to facilitate failure analysis and track their progress.

Building on the coverage theme, our next article by Roger Sabbagh and Harry Foster, "Using Formal Technology to Improve Coverage Results," gives a great overview of the problem of coverage holes and shows how formal technology can be used to automatically improve coverage results while reducing the amount of time wasted trying to hit unreachable states.

In our Consultants' Corner this issue, my friend Ray Salemi, a Senior Verification Consultant here at Mentor, shows how a UVM user can hide the details of what's involved in putting a UVM test together (including sequences, etc.) so that the actual test write has a much simpler API with which to work.

Last but not least, my colleagues Ashish Aggarwal and Ravindra Aneja tie everything together in "A Methodology for Advanced Block-Level Verification." This article neatly summarizes the four major categories of a typical block-level project: RTL development, protocol interface verification, end-to-end verification via simulation and coverage closure. I think you'll agree that this wrap-up does a nice job of contextualizing some of the technologies covered in the previous articles.

Well, I stopped by my house last night to see how the floors are progressing. Everything looks great, and the plastic over everything provides a whole new perspective on "coverage closure." I hope you enjoy this issue of Verification Horizons and hope to see you at DVCon.

Respectfully submitted,
Tom Fitzpatrick
Editor, Verification Horizons


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