Specification to Realization flow using ISequenceSpec™ and Questa® inFact
10:00 AM | Anupam Bakshi - Agnisys, Inc.
Using an Ethernet Controller design, we show how complete verification can be done in an automated manner, saving time while improving quality. Integration of two tools will be shown. InFact creates tests for a variety of scenarios which is more efficient and exhaustive than a pure constrained random methodology. ISequenceSpec forms a layer of abstraction around the IP/SoC from a specification.
Verification IP and Memory Models Improve Productivity and Reduce Risk
11:00 AM | Mark Olen - Mentor Graphics
Many designs incorporate standard interfaces, such as ARM® AMBA®, DisplayPortTM, DDR DRAM, Ethernet, Flash Memory, HDMI®, MIPI, PCIe®, USB and more, that can put a strain on the verification process. Building verification IP for these standards can be a complex process, and takes valuable time away from writing design-specific tests. This session illustrates how many companies are improving their productivity by moving to third-party verification IP and memory models, complete with protocol checks, coverage models, and compliance test suites.
UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs
1:00 PM | Gordon Allan - Mentor Graphics
Is your UVM testbench draining your productivity? Complexity pain and difficulty figuring out what's going on?
- Learn how to solve the top 10 common UVM bringup issues in areas such as the config_db, the factory, and sequence execution.
- Find out how to navigate complex UVM environments, quickly find your way around the code, whether your own or inherited.
- See what's going on in your testbench - how to debug dynamic class activity in SV/UVM alongside RTL signals.
Cadence and Mentor Demonstrate Collaboration for open Debug Data API in Action
2:00 PM | Dave Rich - Mentor Graphics
The Debug Data API is a modernized way to share waveform information than VCD. If VCD still works for you, don’t worry, we are not doing anything to change that flow. The industry has invested decades in access methods for live simulation, but common post simulation results data access has been generally limited to ASCII file dumps in the VCD or eVCD format that have reached their end-of-life. We are looking to extend and augment a traditional live simulation vpi-scheme with one that works for post simulation run datasets as well. You are invited to join us to get an update on the current status of the Debug Data API development and projected timeline of support. We will demonstrate use of the Debug Data API to create debug applications written in C/C++ running on early prototypes from Mentor and Cadence.
Various Methods for Debugging Software in Emulation
3:00 PM | Russ Klein - Mentor Graphics
The Mentor Veloce emulation platform combined with the Questa verification solution can run designs in RTL orders of magnitude faster than simulation alone. As a result, emulation is used to execute verification runs that would be otherwise impossible in logic simulation. Often these verification runs include some software executing on the design – as software is taking an increasing role in the functionality of a System-on-Chip (SoC). With significant software being executed in the context of the verification run, there needs to be some way to debug it. This session covers the various methods provided for debugging software in the context of emulation.
Get Ready for Portable Stimulus
4:00 PM | Tom Fitzpatrick - Mentor Graphics
It sounds like an impossible task. How can you have a single stimulus description that can drive everything from a UVM test in simulation to C++ code in an emulator to a bare metal test post-silicon? The answer is the new Portable Stimulus standard being worked on in Accellera, but the question isn't "how can one specification be all things to everyone?" This session will clearly explain what Portable Stimulus is (and what it isn't), how the Portable Stimulus Working Group is tackling the problem, and what the solution is likely to be. Get the latest information about this exciting new frontier in functional verification from an expert who's been involved in the standard from its inception and learn how you'll be able to use it in your verification environment.
Formal Verification Tips & Tricks for Fun & Profit
5:00 PM | Doug Smith - Mentor Graphics
Join us to learn SVA coding tricks that get the most out of the formal analysis engines AND ensure reuse with simulation and emulation, simple tips to setup the analysis for rapidly reaching a solution, and benefiting from "coverage" in a formal context.
Register for Tuesday's sessions.
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