Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Three CDC Glitches - 5/18
      • User2User - 5/26
      • Fast & Productive USB4 - 6/2
      • Verification Forum - Multiple Dates in June
      • Webinar Calendar

    • On-Demand Webinars

      • Optimizing Constraints
      • Fault Campaign for Mixed-Signal
      • Low Power Verification
      • CDC+RDC Analysis
      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • All On-Demand Webinars

    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings

    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa Basic
      • Questa Advanced
      • Mastering Questa
  • Home
  • Rich Edelman Verification Technologist

Rich Edelman Verification Technologist

Rich Edelman - Verification Technologist

Bio

Verification Technologist

Rich graduated from Washington University in St. Louis, Missouri, with a Bachelor of Science in Computer Science, a Bachelor of Science in Electrical Engineering, and a Master of Science in Computer Science.

Rich has worked at many EDA startups and non-startups and now works for Siemens EDA in Fremont, CA as a Verification Technologist helping verification teams develop successful debug techniques for UVM and class based testbenches.

Rich's previous work includes Register verification, SystemVerilog DPI development and transaction recording interfaces for Questa.

Subject Matter Experts

Harry Foster
Tom Fitzpatrick
Chris Spear
Rich Edelman
Gordon Allan
Jonathan Craft
Ping Yeung
Dave Rich
Kurt Takara
Joe Hupcey
Neil Johnson
Darron May
Mark Eslinger
Adam Erickson
Mark Olen
Jason Polychronopoulos
Matthew Ballance
Moses Satyasekaran
Byran Ramirez
Athira Panicker
Jacob Wiltgen
Chris Giles
Shubhankar Deshmukh
Kamlesh Mulchandani
Bob Oden
Charles Battikha
Doug Smith
Tomasz Piekarz
Mark Peryer
Atul Sharma
Pradeep Salla
Sumit Vishwakarma
Steve Geisler
Hirak Roy
Kaushal Pathak
Progyna Khondkar
Joon Hong
Thomas Ellis
Stephen Bailey
Tom Kiley
Raghu Ardeishar
Dr. Jeremy Levitt
Dave Aerne
Avidan Efody
Geir Eide
Jin Hou
Ray Salemi
Walter Gude
Byron Brinson
Hans Van Der Schoot
Michael Horn
Russ Klein
John Stickley
Vijay Chobisa
Dominic Lucido
Sathish Balasubramanian
Vinayak Desai
Dr. Ashish Darbari
Cliff Cummings
Gordon Walker
Munish Goyal
Brian Craw
Ashish Amonkar
Andreas Meyer
Lee Harrison
Srikanth Rengarajan
Ram Narayan
Rick Koster
Larry Lapides
Marc Schmitz
Kartik Raju
Qazi Ahmed
Harmel Sangha
Sriram Hariharan
Shantanu Samant
Sanjay Gupta
Jim Lewis
John Aynsley
Anupam Bakshi
Dr. Mike Bartley
Vahid Naraghi
Vigyan Singhal
Jin Zhang
Mitchell Poplingher
Niraj Mathur
Dinesh Tyagi
Ellie Burns
Akshay Sarup
Peet James
Ivan Ristic
Peter Wang
Brian Mathewson
Adam Rose
Chuck Seeley
Erich Marschner
Ahmed Eisawy
Verification Academy

Authored Resources

Featured Sessions

  • Making Your DPI-C Interface A Fast River Of Data
  • I Didn’t Know Visualizer Could Do That
  • Introduction to Visualizer for the VHDL Users
  • Introduction to Visualizer for the Verilog Users
  • Better UVM Debug with Visualizer
  • Context-Aware Debug for Complex Heterogeneous Environments
  • Better UVM Debug with Visualizer
  • Debugging Your Design in a Heterogeneous Environment
  • UVM Debug? Beyond Logfiles
  • Goldilocks and System Performance Modeling
  • Are You Smarter Than Your Testbench? With a Little Work You Can Be
  • Verification and Debug: Old School Meets New School

Technical Papers

  • Transaction Recording Anywhere Anytime
  • UVM IEEE Shiny Object
  • DPI Redux. Functionality. Speed. Optimization.
  • No RTL Yet? No Problem - UVM Testing a SystemVerilog Fabric Model
  • UVM Sans UVM - An approach to automating UVM testbench writing
  • Beyond UVM Registers - Better, Faster, Smarter
  • Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
  • Are You Smarter Than Your Testbench? With a Little Work You Can Be

Verification Horizons

  • Fun with UVM Sequences - Coding and Debugging
  • No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model

Resources

  • Verification Horizons Blog
Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 547 3000

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy