Verification Academy

Search form

Use Exact Matching.

My Account Menu

Register
Log In

Topics
Courses
Forums
Patterns Library
Cookbooks
Events
More

All Topics

The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
- Languages & Standards
- Methodologies
- Techniques & Tools
All Courses

The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
- Universal Verification Methodology (UVM)
- Featured Courses
- Additional Courses
- Formal-Based Techniques
- Analog/Mixed Signal
All Forum Topics

The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
- UVM Forum
- SystemVerilog Forum
- Coverage Forum
- Additional Forums
Patterns Library

The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
- Implementation Patterns
- Specification Patterns
- Pattern Resources
All Cookbooks

Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
All Events

No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
About Verification Academy

The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
- Blog & News
- Verification Horizons Publication
- About Us
- Training

Home
Rich Edelman Product Engineer

Rich Edelman Product Engineer

Bio

Product Engineer

Rich Edelman is a Product Engineer at Siemens EDA for the Visualizer Debug Environment. He is a verification technologist helping customers adopt successful techniques for UVM and class based testbenches. Rich previous work includes register verification, SystemVerilog DPI development and transaction recording interfaces for Questa. Rich graduated from Washington University in St. Louis with a bachelor's degree in Computer Science, a bachelor's degree in electrical engineering and a master's degree in computer science.