Peter Wang is currently the Marvell QVIP UVM Verification Platform Project Leader for PHY chip verification. He has over 15 years of experience designing and verifying ASICs & ARM based SOCs. Currently he is focused on the UVM Design Verification for Marvell PHY chips. He has published multiple papers of ASIC UVM design verification on IEEE publications and was a special invited speaker in the 2017 Mentor QVIP international users forum. Previously to Marvell, he was a principle ASIC engineer at Broadcom, SoC Architecture Engineer at Intel Corporation, and a project leader for multiple SoC starting-up companies.
