Michael Horn is a Principal Verification Architect at Siemens EDA specializing in helping ASIC and FPGA groups and companies to deploy UVM and OVM. He started his career in the telecom and storage industries doing design and verification. He has been using high level verification languages since 1999 starting with Specman E then moving to Vera and now SystemVerilog. Michael has co-authored numerous publications and conference papers including papers for DVCon. He received his BSEE from the University of Illinois at Urbana-Champaign.
