Mark Peryer is a Verification Methodologist within the Design Verification and Technology division at Siemens EDA and is responsible for developing and deploying verification methodologies and solutions. He developed his first verification environment for a graphics processor in the mid-eighties and although the languages and the techniques have changed, he has continued to work on hairy verification problems ever since. Mark is the author of many conference papers, articles and training classes and holds an honors degree in Electronic Engineering from Southampton University.
