Graeme Jessiman is an Applications Engineering Team Leader at Siemens EDA based in Scotland. For over 25 years he has supported Siemens simulation and static/formal tools for European customers spanning many different industry segments. One key area has been helping VHDL customer adopt advanced verification methodologies such as UVMF. Graeme hold as BSc (Hons) in Electrical and Electronic Engineering from the Robert Gordon University in Aberdeen, is a Chartered Engineer and a member of the IET.