Avidan Efody is a verification architect for Siemens EDA, and an expert in listening to customers, distilling their problems, and helping them get to the optimal solution, preferably using Siemens EDA tools. Prior to moving to EDA Avidan has been architecting and coding testbenches in a variety of languages/methodologies for a variety of companies including PMC-Sierra, Infineon, TI, Nokia-Siemens and others. Recent problems he has been called to solve are fault analysis according to ISO 26262 specification, removal of adoption barriers for advanced verification methodologies within ISO 26262 and DO 254 flows, AMBA interconnect verification, Matlab-RTL integration and a few more. He’s proficient in SystemVerilog, OVM, UVM and a multitude of scripting languages such as Perl, TCL, PHP and JavaScript.
